`include "cpu_pkg.svh"

import cpu_pkg::*;

module alu (
    input logic       clk_i,
    input logic       nreset_i,

    input logic       alu_op_valid_i,
    input alu_op_t    alu_op_i,
    input logic [7:0] operand_i,
    input logic [2:0] inx8_i, // Only used for bit/set/res

    input alu16_op_t   alu16_op_i,
    input logic [15:0] inx16_i,
    input logic [15:0] iny16_i,

    output logic [ 7:0] a_o,
    output logic [ 7:0] f_o,

    output logic [15:0] out16_o
);

    logic        a_we;
    logic [ 7:0] a_r;
    logic [ 7:0] a_next;

    logic        f_we;
    logic [ 7:0] f_r;
    logic [ 7:0] f_next;

    logic [ 7:0] a_xor;
    logic [ 7:0] f_xor;

    logic [ 7:0] a_bit; // Never written, only to test
    logic [ 7:0] f_bit;

    logic [16:0] out16_add;
    logic [ 7:0] f16_add;
    logic [15:0] out16_inc;
    logic [15:0] out16_dec;

    `DEF_FF(a_r, a_next, a_we, '0);
    `DEF_FF(f_r, f_next, f_we, '0);

    assign a_we   = alu_op_valid_i;
    assign a_next = (alu_op_i == ALU_OP_XOR) ? a_xor     :
                    (alu_op_i == ALU_OP_NOP) ? operand_i :
                                               a_r;

    assign f_we   = alu_op_valid_i;
    assign f_next = (alu_op_i == ALU_OP_XOR) ? f_xor :
                    (alu_op_i == ALU_OP_BIT) ? f_bit :
                                               f_r;

    assign a_xor = (a_r ^ operand_i);
    assign f_xor = {~(|a_xor), 3'b0, f_r[3:0]};

    assign a_bit = (operand_i - {4'b0, inx8_i});
    assign f_bit = {~(|a_bit), 2'b10, f_r[4:0]};

    assign out16_dec = (inx16_i - 16'h01);

    assign a_o = a_r;
    assign f_o = f_r;

    assign out16_o = out16_dec;

endmodule : alu