module decode (
    input  [7:0] instr0_i,
    input  [7:0] instr1_i,
    input  [7:0] instr2_i,

    output logic need_instr1_o,
    output logic need_instr2_o,
    output logic undef_o
);

    logic is_ld_sp_nnnn;


    assign is_ld_sp_nnnn = (instr0_i == 7'h31);

    assign need_instr1_o = is_ld_sp_nnnn;
    assign need_instr2_o = is_ld_sp_nnnn;

    assign undef_o = ~is_ld_sp_nnnn;

endmodule : decode