module gb (
    input  logic clk_i,
    input  logic nreset_i
);

    logic        we;
    logic [15:0] address;
    logic [ 7:0] rdata;
    logic [ 7:0] wdata;

    logic        rom_cs;
    logic [ 7:0] rom_rdata;

    logic        hi_ram_cs;
    logic [ 7:0] hi_ram_rdata;

    cpu cpu_inst (
        .clk_i    (clk_i),
        .nreset_i (nreset_i),
        .address_o(address),
        .rdata_i  (rdata),
        .we_o     (we),
        .wdata_o  (wdata)
    );

    rom #(
        .FILE_NAME("DMG_ROM.bin"),
        .ADDR_W   (8),
        .DATA_W   (8)
    ) rom_inst (
        .clk_i    (clk_i),
        .cs_i     (rom_cs),
        .address_i(address[7:0]),
        .rdata_o  (rom_rdata)
    );

    ram #(
        .ADDR_W (7),
        .DATA_W (8)
    ) hi_ram_inst (
        .clk_i     (clk_i),
        .cs_i      (hi_ram_cs),
        .address_i (address[6:0]),
        .rdata_o   (hi_ram_rdata),
        .we_i      (we),
        .wdata_i   (wdata)
    );

    assign rom_cs    = ~(|address[15:8]);
    assign hi_ram_cs = (&address[15:7]) & ~(&address[6:0]);

    assign rdata = rom_rdata | hi_ram_rdata;

endmodule : gb