module ram #(
    parameter DATA_W = 8,
    parameter ADDR_W = 8
)(
    input  logic              clk_i,

    input  logic              cs_i,

    input  logic [ADDR_W-1:0] address_i,
    input  logic              we_i,
    input  logic [DATA_W-1:0] wdata_i,
    output logic [DATA_W-1:0] rdata_o
);

localparam RAM_SIZE = 2**ADDR_W;

logic [DATA_W-1:0] ram [RAM_SIZE-1:0];

logic              wenable;
logic [DATA_W-1:0] rdata;

assign wenable = cs_i & we_i;

always_ff @(posedge clk_i)
    if (wenable)
        ram[address_i] <= wdata_i;

always_ff @(posedge clk_i)
    if (cs_i)
        rdata <= ram[address_i];

assign rdata_o = {DATA_W{cs_i}} & rdata;

endmodule