module ppu (
  input  logic clk,
  input  logic nreset,

  input  logic [15:0] cpu_addr_i,
  output logic [ 7:0] cpu_rdata_o,
  input  logic        cpu_we_i,
  input  logic [ 7:0] cpu_wdata_i,

  output logic        cpu_addr_sel_o
);

logic ly_sel;

logic ly_r;
logic ly_we;

assign ly_sel = (cpu_addr_i == 16'hFF44);
assign ly_we  = ly_sel & cpu_we_i;

always_ff @(posedge clk or negedge nreset) begin
  if (!nreset)
    ly_r <= 8'h90; // vsync hack
  else if (ly_we)
    ly_r <= 8'h90;
end

assign cpu_addr_sel_o = ly_sel;

endmodule : ppu