48 lines
1.3 KiB
Systemverilog
48 lines
1.3 KiB
Systemverilog
module vgasim #(
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parameter SCREEN_H = 640,
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parameter SCREEN_W = 480,
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parameter DEPTH = 8
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) (
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input logic clk,
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input logic nreset,
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input logic [DEPTH-1:0] r_i,
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input logic [DEPTH-1:0] g_i,
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input logic [DEPTH-1:0] b_i,
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input logic hsync_i,
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input logic vsync_i
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);
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import "DPI-C" function int vgasim_init(input int screen_h, input int screen_w, input int screen_bpp);
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import "DPI-C" function int vgasim_reset();
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import "DPI-C" function int vgasim_tick(input int r, input int g, input int b, input int hsync, input int vsync);
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logic vgasim_initialised = 0;
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initial begin
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automatic int ret = vgasim_init(SCREEN_W, SCREEN_H, DEPTH);
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if (ret != 0) begin
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$display($sformatf("[%0t] vgasim init failed: %d", $time, ret));
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end else begin
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vgasim_initialised = '1;
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end
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end
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always @(negedge nreset iff vgasim_initialised) begin
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automatic int ret = vgasim_reset();
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assert (ret == 0) else begin
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$display($sformatf("[%0t] vgasim reset failed: %d", $time, ret));
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$fatal();
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end
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end
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always @(posedge clk iff nreset && vgasim_initialised) begin
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automatic int ret = vgasim_tick(r_i, g_i, b_i, hsync_i, vsync_i);
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assert (ret == 0) else begin
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$display($sformatf("[%0t] vgasim tick failed: %d", $time, ret));
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$fatal();
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end
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end
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endmodule : vgasim
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