Koray Yanik
fda176d3b5
Rewrite to use several bus multiplexers, resulting into a less messy microarchitecture (hopefully). Some more room for cleanup though... Supports every instruction from the bootstrap rom, more or less. LY hacked at 0x90 to progress through vsync instantly. No cartridge is present yet, so we will always fail checksum test and lock up.
19 lines
245 B
Systemverilog
19 lines
245 B
Systemverilog
module clkgen #(
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PERIOD_NS = 10,
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RESET_DELAY_NS = 45
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) (
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output logic clk,
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output logic nreset
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);
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initial begin
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clk <= 1'b1;
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nreset <= 1'b0;
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#RESET_DELAY_NS nreset <= 1'b1;
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end
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always
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#(PERIOD_NS/2) clk <= ~clk;
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endmodule
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