103 lines
2.5 KiB
Systemverilog
103 lines
2.5 KiB
Systemverilog
`include "cpu_pkg.svh"
|
|
|
|
import cpu_pkg::*;
|
|
|
|
module cpu (
|
|
input logic clk_i,
|
|
input logic nreset_i,
|
|
|
|
output logic [15:0] address_o,
|
|
input logic [ 7:0] rdata_i
|
|
);
|
|
|
|
state_t state;
|
|
|
|
logic alu_op_valid;
|
|
alu_op_t alu_op;
|
|
op_src_t op_src;
|
|
op_dest_t op_dest;
|
|
|
|
logic [ 7:0] alu_operand;
|
|
|
|
logic [ 7:0] rega;
|
|
logic [ 7:0] regf;
|
|
|
|
logic [15:0] pc;
|
|
logic [15:0] sp;
|
|
|
|
logic instr_valid;
|
|
logic instr_undef;
|
|
|
|
logic [ 7:0] operand8;
|
|
logic [15:0] operand16;
|
|
|
|
reg8_t reg8_wselect;
|
|
logic reg8_we;
|
|
logic [ 7:0] reg8_wdata;
|
|
reg16_t reg16_wselect;
|
|
logic reg16_we;
|
|
logic [15:0] reg16_wdata;
|
|
reg8_t reg8_rselect;
|
|
reg16_t reg16_rselect;
|
|
logic [ 7:0] reg8_rdata;
|
|
logic [15:0] reg16_rdata;
|
|
|
|
control control_inst (
|
|
.clk_i (clk_i),
|
|
.nreset_i (nreset_i),
|
|
.rdata_i (rdata_i),
|
|
.state_o (state),
|
|
.pc_o (pc),
|
|
.sp_o (sp),
|
|
.alu_op_valid_o(alu_op_valid),
|
|
.alu_op_o (alu_op),
|
|
.op_src_o (op_src),
|
|
.op_dest_o (op_dest),
|
|
.instr_valid_o (instr_valid),
|
|
.instr_undef_o (instr_undef),
|
|
.operand8_o (operand8),
|
|
.operand16_o (operand16),
|
|
.reg16_dest_o (reg16_wselect)
|
|
);
|
|
|
|
alu alu_inst (
|
|
.clk_i (clk_i),
|
|
.nreset_i (nreset_i),
|
|
.alu_op_valid_i(alu_op_valid),
|
|
.alu_op_i (alu_op),
|
|
.operand_i (alu_operand),
|
|
.a_o (rega),
|
|
.f_o (regf)
|
|
);
|
|
|
|
registers registers_inst (
|
|
.clk_i (clk_i),
|
|
.nreset_i(nreset_i),
|
|
|
|
.reg8_wselect_i (reg8_wselect),
|
|
.reg8_we_i (reg8_we),
|
|
.reg8_wdata_i (reg8_wdata),
|
|
.reg16_wselect_i(reg16_wselect),
|
|
.reg16_we_i (reg16_we),
|
|
.reg16_wdata_i (reg16_wdata),
|
|
.reg8_rselect_i (reg8_rselect),
|
|
.reg8_rdata_o (reg8_rdata),
|
|
.reg16_rselect_i(reg16_rselect),
|
|
.reg16_rdata_o (reg16_rdata)
|
|
);
|
|
|
|
assign alu_operand = (op_src == OP_SRC_A) ? rega :
|
|
'0;
|
|
|
|
assign reg8_wselect = reg8_t'('X);
|
|
assign reg8_we = '0;
|
|
assign reg8_wdata = operand8;
|
|
assign reg16_we = instr_valid & (op_dest == OP_DEST_R16);
|
|
assign reg16_wdata = operand16;
|
|
assign reg8_rselect = reg8_t'('X);
|
|
assign reg16_rselect = reg16_t'('X);
|
|
|
|
assign address_o = pc;
|
|
|
|
endmodule : cpu
|