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3191a19f7e
svgb
/
rtl
/
cpu
/
cpu_pkg.svh
11 lines
138 B
Systemverilog
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package
cpu_pkg
;
typedef
enum
{
ST0_ADDR
,
ST1_DEC
,
ST2_EXEC
,
ST3_INC_ADDR
}
state_t
;
endpackage
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