71 lines
1.9 KiB
Systemverilog
71 lines
1.9 KiB
Systemverilog
`include "cpu_pkg.svh"
|
|
|
|
import cpu_pkg::*;
|
|
|
|
module decode (
|
|
input logic [7:0] instr0_i,
|
|
input logic [7:0] instr1_i,
|
|
input logic [7:0] instr2_i,
|
|
|
|
input state_t state_i,
|
|
|
|
output logic need_instr1_o,
|
|
output logic need_instr2_o,
|
|
output logic undef_o,
|
|
|
|
output logic sp_we_o,
|
|
output sp_src_t sp_src_o,
|
|
|
|
output logic alu_op_valid_o,
|
|
output alu_op_t alu_op_o,
|
|
output op_src_t op_src_o,
|
|
output op_dest_t op_dest_o,
|
|
|
|
output reg16_t reg16_dest_o,
|
|
|
|
output adr_src_t adr_src_o
|
|
);
|
|
|
|
logic [1:0] dec_x;
|
|
logic [2:0] dec_y;
|
|
logic [2:0] dec_z;
|
|
logic [1:0] dec_p;
|
|
logic dec_q;
|
|
|
|
logic is_ld_rr_nnnn;
|
|
logic is_ld_sp_nnnn;
|
|
logic is_alu_a_n;
|
|
|
|
assign dec_x = instr0_i[7:6];
|
|
assign dec_y = instr0_i[5:3];
|
|
assign dec_z = instr0_i[2:0];
|
|
assign dec_p = instr0_i[5:4];
|
|
assign dec_q = instr0_i[3];
|
|
|
|
assign is_ld_rr_nnnn = (dec_x == 2'h0) & (dec_z == 3'h1) & ~dec_q & (dec_p != 2'h3);
|
|
assign is_ld_sp_nnnn = (dec_x == 2'h0) & (dec_z == 3'h1) & ~dec_q & (dec_p == 2'h3);
|
|
|
|
assign is_alu_a_n = (dec_x == 3'h2);
|
|
|
|
assign need_instr1_o = is_ld_sp_nnnn | is_ld_rr_nnnn;
|
|
assign need_instr2_o = is_ld_sp_nnnn | is_ld_rr_nnnn;
|
|
|
|
assign undef_o = ~(is_ld_sp_nnnn | is_ld_rr_nnnn | is_alu_a_n);
|
|
|
|
assign sp_we_o = is_ld_sp_nnnn & (state_i == ST4_EXEC);
|
|
|
|
assign alu_op_valid_o = is_alu_a_n;
|
|
assign alu_op_o = alu_op_t'(dec_y);
|
|
assign op_dest_o = is_alu_a_n ? OP_DEST_A :
|
|
is_ld_rr_nnnn ? OP_DEST_R16 :
|
|
op_dest_t'('X);
|
|
|
|
assign op_src_o = is_alu_a_n ? OP_SRC_REG8 :
|
|
is_ld_rr_nnnn ? OP_SRC_OPERAND16 :
|
|
op_src_t'('X);
|
|
|
|
assign reg16_dest_o = reg16_t'(dec_p);
|
|
|
|
assign adr_src_o = ADR_SRC_PC;
|
|
|
|
endmodule : decode |