96 lines
2.7 KiB
Systemverilog
96 lines
2.7 KiB
Systemverilog
`include "cpu_pkg.svh"
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import cpu_pkg::*;
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module alu (
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input logic clk_i,
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input logic nreset_i,
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input logic alu_op_valid_i,
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input alu_op_t alu_op_i,
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input logic [7:0] operand_i,
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input logic [2:0] inx8_i, // Only used for bit/set/res
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input logic rot_op_valid_i,
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input rot_op_t rot_op_i,
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input alu16_op_t alu16_op_i,
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input logic [15:0] inx16_i,
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input logic [15:0] iny16_i,
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output logic [ 7:0] a_o,
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output logic [ 7:0] f_o,
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output logic [ 7:0] out8_o, // Only used for inc/dec reg8 and rot
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output logic [15:0] out16_o
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);
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logic a_we;
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logic [ 7:0] a_r;
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logic [ 7:0] a_next;
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logic f_we;
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logic [ 7:0] f_r;
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logic [ 7:0] f_next;
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logic [ 7:0] a_inc;
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logic [ 7:0] f_inc;
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logic [ 7:0] a_xor;
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logic [ 7:0] f_xor;
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logic [ 7:0] a_bit; // Never written, only to test
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logic [ 7:0] f_bit;
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logic [ 7:0] out8_incr;
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logic [ 7:0] f_incr;
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logic [ 7:0] out8_rl;
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logic [ 7:0] f_rl;
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logic [15:0] out16_inc;
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logic [15:0] out16_dec;
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`DEF_FF(a_r, a_next, a_we, '0);
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`DEF_FF(f_r, f_next, f_we, '0);
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assign a_we = alu_op_valid_i;
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assign a_next = (alu_op_valid_i & (alu_op_i == ALU_OP_XOR)) ? a_xor :
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(alu_op_valid_i & (alu_op_i == ALU_OP_NOP)) ? operand_i :
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(alu_op_valid_i & (alu_op_i == ALU_OP_INC)) ? a_inc :
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a_r;
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assign f_we = alu_op_valid_i | rot_op_valid_i;
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assign f_next = (alu_op_valid_i & (alu_op_i == ALU_OP_XOR)) ? f_xor :
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(alu_op_valid_i & (alu_op_i == ALU_OP_BIT)) ? f_bit :
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(alu_op_valid_i & (alu_op_i == ALU_OP_INC)) ? f_inc :
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(alu_op_valid_i & (alu_op_i == ALU_OP_INCR)) ? f_incr :
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(rot_op_valid_i & (rot_op_i == ROT_OP_RL)) ? f_rl :
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f_r;
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assign a_xor = (a_r ^ operand_i);
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assign f_xor = {~(|a_xor), 3'b0, f_r[3:0]};
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assign a_inc = (a_r + 8'h01);
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assign f_inc = {~(|a_inc), 1'b0, a_inc[4], f_r[3:0]};
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assign a_bit = (operand_i - {4'b0, inx8_i});
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assign f_bit = {~(|a_bit), 2'b10, f_r[4:0]};
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assign out8_rl = {operand_i[6:0], f_r[4]};
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assign f_rl = {~(|out8_rl), 2'b0, operand_i[7], f_r[3:0]};
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assign out8_incr = (operand_i + 8'h01);
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assign f_incr = {~(|out8_incr), 1'b0, out8_incr[4], f_r[3:0]};
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assign out16_dec = (inx16_i - 16'h01);
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assign a_o = a_r;
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assign f_o = f_r;
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assign out8_o = ({8{alu_op_valid_i}} & out8_incr) | {8{rot_op_valid_i}} & out8_rl;
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assign out16_o = out16_dec;
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endmodule : alu |