51 lines
1.4 KiB
Systemverilog
51 lines
1.4 KiB
Systemverilog
module tb_top ();
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logic clk;
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logic nreset;
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clkgen clkgen_inst (
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.clk_o (clk),
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.nreset_o(nreset)
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);
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gb gb_inst (
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.clk_i (clk),
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.nreset_i(nreset)
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);
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// Testbench code
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logic instr_undef;
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logic halted;
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logic [15:0] last_pc;
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logic [ 7:0] last_opcode;
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logic [ 7:0] last_op1;
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logic [ 7:0] last_op2;
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logic we;
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logic [15:0] address;
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logic [ 7:0] wdata;
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assign halted = gb_inst.cpu_inst.control_inst.halted_r;
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assign instr_undef = gb_inst.cpu_inst.control_inst.is_undef;
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assign last_pc = gb_inst.cpu_inst.control_inst.instr_pc_r;
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assign last_opcode = gb_inst.cpu_inst.control_inst.instr_r;
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assign last_op1 = gb_inst.cpu_inst.control_inst.operand0_r;
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assign last_op2 = gb_inst.cpu_inst.control_inst.operand1_r;
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assign we = gb_inst.we;
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assign address = gb_inst.address;
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assign wdata = gb_inst.wdata;
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always @(posedge clk) begin
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if (nreset && instr_undef & ~halted) begin
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$display($sformatf("[%0t] %X: Undefined opcode %X | [%X | %X]", $time(), last_pc, last_opcode, last_op1, last_op2));
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$fatal(0);
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$finish();
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end
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if (nreset && we) begin
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$display($sformatf("[%0t] Write: [%X] <= %X", $time(), address, wdata));
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end
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end
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endmodule : tb_top
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