64 lines
2.0 KiB
Systemverilog
64 lines
2.0 KiB
Systemverilog
`include "cpu_pkg.svh"
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import cpu_pkg::*;
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module registers (
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input logic clk_i,
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input logic nreset_i,
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input reg8_t reg8_wselect_i,
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input logic reg8_we_i,
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input logic [ 7:0] reg8_wdata_i,
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input reg16_t reg16_wselect_i,
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input logic reg16_we_i,
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input logic [15:0] reg16_wdata_i,
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input reg8_t reg8_rselect_i,
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input reg16_t reg16_rselect_i,
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input reg16_t reg16_rselect2_i,
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output logic [ 7:0] reg8_rdata_o,
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output logic [15:0] reg16_rdata_o,
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output logic [15:0] reg16_rdata2_o,
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output logic [15:0] hl_o
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);
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logic [15:0] reg_r [0:2];
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logic [15:0] reg_next;
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logic [ 1:0] reg_we [0:2];
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generate for (genvar i = 0; i <= 2; i++) begin : gen_regs
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always_ff @(posedge clk_i or negedge nreset_i) begin
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if (~nreset_i) begin
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reg_r[i][7:0] <= '0;
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end else if (reg_we[i][0]) begin
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reg_r[i][7:0] <= reg_next[7:0];
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end
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end
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always_ff @(posedge clk_i or negedge nreset_i) begin
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if (~nreset_i) begin
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reg_r[i][15:8] <= '0;
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end else if (reg_we[i][1]) begin
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reg_r[i][15:8] <= reg_next[15:8];
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end
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end
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assign reg_we[i][0] = (reg16_we_i & (reg16_wselect_i == i)) |
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(reg8_we_i & ({reg8_wselect_i, 1'b0} == i));
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assign reg_we[i][1] = (reg16_we_i & (reg16_wselect_i == i)) |
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(reg8_we_i & ({reg8_wselect_i, 1'b1} == i));
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end endgenerate
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assign reg_next = ({16{reg8_we_i}} & {reg8_wdata_i, reg8_wdata_i}) |
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({16{reg16_we_i}} & reg16_wdata_i);
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assign reg8_rdata_o = reg8_rselect_i[0] ? reg_r[reg8_rselect_i[2:1]][15:8] :
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reg_r[reg8_rselect_i[2:1]][ 7:0];
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assign reg16_rdata_o = reg_r[reg16_rselect_i];
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assign reg16_rdata2_o = reg_r[reg16_rselect2_i];
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assign hl_o = reg_r[REG16_HL];
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endmodule : registers
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