19 lines
308 B
Systemverilog
19 lines
308 B
Systemverilog
module clkgen #(
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PERIOD_NS = 10,
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RESET_DELAY_NS = 100
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) (
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output logic clk_o,
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output logic nreset_o
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);
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initial begin
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clk_o <= 1'b1;
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nreset_o <= 1'b0;
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#RESET_DELAY_NS nreset_o <= 1'b1;
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end
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always
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#(PERIOD_NS/2) clk_o <= ~clk_o;
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endmodule
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