152 lines
3.9 KiB
Systemverilog
152 lines
3.9 KiB
Systemverilog
`define VSYNC_HACK
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module ppu (
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input logic clk,
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input logic nreset,
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output logic display_enable_o,
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input logic [15:0] cpu_addr_i,
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output logic [ 7:0] cpu_rdata_o,
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input logic cpu_we_i,
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input logic [ 7:0] cpu_wdata_i,
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output logic [15:0] ppu_addr_o,
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input logic [ 7:0] ppu_rdata_i,
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output logic [ 1:0] pixel_o,
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output logic vsync_o,
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output logic hsync_o
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);
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`define REG_DECL(t, name) \
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t name``_r; \
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t name``_next; \
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logic name``_we;
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`define REG_DEF(name, rstval) \
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always_ff @(posedge clk or negedge nreset) begin \
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if (!nreset) \
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name``_r <= rstval; \
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else if (name``_we) \
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name``_r <= name``_next; \
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end
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typedef enum {
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ST_RESET,
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ST_OAM_SCAN,
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ST_FETCH_TILE_INDEX,
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ST_FETCH_TILE_DATA0,
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ST_FETCH_TILE_DATA1,
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ST_PUSH_PIXELS,
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ST_HBLANK
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} state_t;
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`REG_DECL(state_t, state);
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`REG_DECL(logic [7:0], oam);
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`REG_DECL(logic [7:0], tile);
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`REG_DECL(logic [7:0], tile_no);
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`REG_DECL(logic [7:0], ly);
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logic ly_sel;
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logic ly_end_of_frame;
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logic [ 8:0] lx_r;
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logic [ 8:0] lx_next;
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logic lx_we;
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logic lx_end_of_line;
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logic tilemap_base_sel;
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logic [ 7:0] ioregs_rdata;
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`REG_DEF(state, ST_RESET);
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assign state_we = 1'b1;
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always_comb begin
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state_next = state_r;
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case (state_r)
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ST_RESET: state_next = ST_OAM_SCAN;
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ST_OAM_SCAN: state_next = oam_we ? ST_OAM_SCAN : ST_FETCH_TILE_INDEX; // 80 cycles per row
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ST_FETCH_TILE_INDEX: state_next = ST_FETCH_TILE_DATA0; // 1 cycle x 20 per row
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ST_FETCH_TILE_DATA0: state_next = ST_FETCH_TILE_DATA1; // 1 cycle x 20 per row
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ST_FETCH_TILE_DATA1: state_next = ST_PUSH_PIXELS; // 1 cycle x 20 per row
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ST_PUSH_PIXELS: state_next = (tile_no_r == 5'd20) ? ST_HBLANK : ST_PUSH_PIXELS; // 8 cycles x 20 per row
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ST_HBLANK: state_next = lx_end_of_line ? ST_FETCH_TILE_INDEX : ST_HBLANK;
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endcase
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end
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`REG_DEF(tile, '0);
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assign tile_we = (state_r == ST_FETCH_TILE_INDEX);
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assign tile_next = ppu_rdata_i;
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`REG_DEF(tile_no, '0);
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assign tile_no_we = (state_next == ST_FETCH_TILE_INDEX);
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assign tile_no_next = (state_r == ST_OAM_SCAN) ? '0 :
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(tile_no_r + 8'h01);
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`REG_DEF(oam, '0)
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assign oam_we = (state_r == ST_OAM_SCAN) & (oam_r < 7'd80);
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assign oam_next = (oam_r + 7'h01);
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`REG_DEF(ly, '0)
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assign ly_sel = (cpu_addr_i == 16'hFF44);
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assign ly_next = (ly_sel & cpu_we_i) ? 8'h00 : // Clear on write
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(lx_end_of_line & ly_end_of_frame) ? 8'h00 :
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(lx_end_of_line & ~ly_end_of_frame) ? (ly_r + 8'h01) :
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ly_r;
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assign ly_end_of_frame = ly_r > 8'd153;
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`REG_DEF(lx, '0)
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assign lx_we = 1'b1;
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assign lx_next = lx_end_of_line ? 9'h0 : (lx_r + 9'h01);
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assign lx_end_of_line = lx_r > 9'd456;
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ppu_ioregs ppu_ioregs_inst (
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.clk (clk),
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.nreset(nreset),
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.cpu_addr_i (cpu_addr_i),
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.cpu_rdata_o(ioregs_rdata),
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.cpu_we_i (cpu_we_i),
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.cpu_wdata_i(cpu_wdata_i),
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.display_enable_o(display_enable_o),
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.tilemap_base_sel_o(tilemap_base_sel)
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);
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assign pixel_o = ((lx_r < 8'd160) & (ly_r < 8'd144)) ? ly_r[1:0] : // should create a nice line-pattern for now
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2'h00;
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assign vsync_o = ly_r >= 8'd144;
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assign hsync_o = lx_r >= 8'd160;
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assign cpu_rdata_o =
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ioregs_rdata |
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`ifdef VSYNC_HACK
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{8{ ly_sel}} & 8'h90;
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`else
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{8{ ly_sel}} & ly_r;
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`endif
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logic [7:0] tilemap_base_addr;
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assign tilemap_base_addr = tilemap_base_sel ? 8'h9C : 8'h98;
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assign ppu_addr_o = {tilemap_base_addr, tile_no_r};//(state_next == ST_FETCH_TILE_INDEX) ? {tilemap_base_addr, tile_no} :
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//(state_next == ST_PUSH_PIXELS & lx_r[])
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`ifdef SVA_ENABLE
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logic sva_sel;
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assign sva_sel = ly_sel;
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`endif /* SVA_ENABLE */
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endmodule : ppu
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