80 lines
1.7 KiB
Systemverilog
80 lines
1.7 KiB
Systemverilog
package cpu_pkg;
|
|
|
|
//
|
|
// 4 | ST0_ADDR -> ST1_DEC -> ST2_EXEC -> ST3_NOP
|
|
// 12 | '-> ST2_DEC -> ST3_DEC -> ST4_EXEC -> .... -> ST11_NOP
|
|
//
|
|
typedef enum {
|
|
ST0_ADDR,
|
|
ST1_DEC,
|
|
ST2_EXEC,
|
|
ST2_DEC,
|
|
ST3_DEC,
|
|
ST4_EXEC
|
|
} state_t;
|
|
|
|
typedef enum logic [2:0] {
|
|
REG8_B = 3'h00,
|
|
REG8_C = 3'h01,
|
|
REG8_D = 3'h02,
|
|
REG8_E = 3'h03,
|
|
REG8_H = 3'h04,
|
|
REG8_L = 3'h05
|
|
} reg8_t;
|
|
|
|
typedef enum logic [1:0] {
|
|
REG16_BC = 2'h00,
|
|
REG16_DE = 2'h01,
|
|
REG16_HL = 2'h02,
|
|
REG16_SP_AF = 2'h03
|
|
} reg16_t;
|
|
|
|
typedef enum logic [2:0] {
|
|
ALU_OP_ADD = 3'h00,
|
|
ALU_OP_ADC = 3'h01,
|
|
ALU_OP_SUB = 3'h02,
|
|
ALU_OP_SBC = 3'h03,
|
|
ALU_OP_AND = 3'h04,
|
|
ALU_OP_XOR = 3'h05,
|
|
ALU_OP_OR = 3'h06,
|
|
ALU_OP_CP = 3'h07
|
|
} alu_op_t;
|
|
|
|
typedef enum logic [1:0] {
|
|
ALU16_OP_ADD = 2'h00,
|
|
ALU16_INC = 2'h01,
|
|
ALU16_DEC = 2'h02
|
|
} alu16_op_t;
|
|
|
|
typedef enum {
|
|
OP_SRC_A,
|
|
OP_SRC_REG8,
|
|
OP_SRC_OPERAND16,
|
|
OP_SRC_REG16
|
|
} op_src_t;
|
|
|
|
typedef enum {
|
|
OP_DEST_A,
|
|
OP_DEST_REG16
|
|
} op_dest_t;
|
|
|
|
typedef enum {
|
|
SP_SRC_OPERAND16
|
|
} sp_src_t;
|
|
|
|
typedef enum {
|
|
ADR_SRC_PC,
|
|
ADR_SRC_HL
|
|
} adr_src_t;
|
|
|
|
endpackage
|
|
|
|
`define DEF_FF(register, next, we, rst_value) \
|
|
always_ff @(posedge clk_i or negedge nreset_i) begin \
|
|
if (~nreset_i) begin \
|
|
register <= (rst_value); \
|
|
end else if ((we)) begin \
|
|
register <= (next); \
|
|
end \
|
|
end
|