68 lines
1.6 KiB
Systemverilog
68 lines
1.6 KiB
Systemverilog
`include "cpu_pkg.svh"
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import cpu_pkg::*;
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module alu (
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input logic clk_i,
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input logic nreset_i,
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input logic alu_op_valid_i,
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input alu_op_t alu_op_i,
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input logic [7:0] operand_i,
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input logic [2:0] inx8_i, // Only used for bit/set/res
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input alu16_op_t alu16_op_i,
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input logic [15:0] inx16_i,
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input logic [15:0] iny16_i,
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output logic [ 7:0] a_o,
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output logic [ 7:0] f_o,
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output logic [15:0] out16_o
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);
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logic a_we;
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logic [ 7:0] a_r;
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logic [ 7:0] a_next;
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logic f_we;
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logic [ 7:0] f_r;
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logic [ 7:0] f_next;
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logic [ 7:0] a_xor;
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logic [ 7:0] f_xor;
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logic [ 7:0] a_bit; // Never written, only to test
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logic [ 7:0] f_bit;
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logic [16:0] out16_add;
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logic [ 7:0] f16_add;
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logic [15:0] out16_inc;
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logic [15:0] out16_dec;
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`DEF_FF(a_r, a_next, a_we, '0);
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`DEF_FF(f_r, f_next, f_we, '0);
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assign a_we = alu_op_valid_i;
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assign a_next = (alu_op_i == ALU_OP_XOR) ? a_xor :
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a_r;
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assign f_we = alu_op_valid_i;
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assign f_next = (alu_op_i == ALU_OP_XOR) ? f_xor :
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(alu_op_i == ALU_OP_BIT) ? f_bit :
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f_r;
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assign a_xor = (a_r ^ operand_i);
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assign f_xor = {~(|a_xor), 3'b0, f_r[3:0]};
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assign a_bit = (operand_i - {4'b0, inx8_i});
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assign f_bit = {~(|a_bit), 2'b10, f_r[4:0]};
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assign out16_dec = (inx16_i - 16'h01);
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assign a_o = a_r;
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assign f_o = f_r;
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assign out16_o = out16_dec;
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endmodule : alu |