33 lines
525 B
Systemverilog
33 lines
525 B
Systemverilog
`include "cpu_pkg.svh"
|
|
|
|
import cpu_pkg::*;
|
|
|
|
module cpu (
|
|
input logic clk_i,
|
|
input logic nreset_i,
|
|
|
|
output logic [15:0] address_o,
|
|
input logic [ 7:0] rdata_i
|
|
);
|
|
|
|
state_t state;
|
|
|
|
logic [15:0] pc;
|
|
|
|
control control_inst (
|
|
.clk_i (clk_i),
|
|
.nreset_i(nreset_i),
|
|
.rdata_i (rdata_i),
|
|
.state_o (state),
|
|
.pc_o (pc)
|
|
);
|
|
|
|
registers registers_inst (
|
|
.clk_i (clk_i),
|
|
.nreset_i(nreset_i)
|
|
);
|
|
|
|
assign address_o = pc;
|
|
|
|
endmodule : cpu
|