25 lines
516 B
Systemverilog
25 lines
516 B
Systemverilog
module rom #(
|
|
parameter string FILE_NAME = "",
|
|
parameter integer unsigned ADDR_W = 8,
|
|
parameter integer unsigned DATA_W = 8
|
|
) (
|
|
input logic clk_i,
|
|
input logic [ADDR_W-1:0] address_i,
|
|
|
|
output logic [DATA_W-1:0] rdata_o
|
|
);
|
|
|
|
localparam ROM_SIZE = 2**ADDR_W;
|
|
|
|
logic [DATA_W-1:0] rom [ROM_SIZE-1:0];
|
|
|
|
always_ff @(posedge clk_i)
|
|
rdata_o <= rom[address_i];
|
|
|
|
initial begin
|
|
static integer fd = $fopen(FILE_NAME, "rb");
|
|
void'($fread(rom, fd));
|
|
end
|
|
|
|
endmodule : rom
|