27 lines
474 B
Systemverilog
27 lines
474 B
Systemverilog
module gb (
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input logic clk_i,
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input logic nreset_i
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);
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logic [15:0] address;
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logic [ 7:0] rdata;
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cpu cpu_inst (
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.clk_i (clk_i),
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.nreset_i (nreset_i),
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.address_o(address),
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.rdata_i (rdata)
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);
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rom #(
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.FILE_NAME("DMG_ROM.bin"),
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.ADDR_W (8),
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.DATA_W (8)
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) rom_inst (
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.clk_i (clk_i),
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.address_i(address[7:0]),
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.rdata_o (rdata)
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);
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endmodule : gb
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