215 lines
6.8 KiB
Systemverilog
215 lines
6.8 KiB
Systemverilog
`include "cpu_pkg.svh"
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import cpu_pkg::*;
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module control (
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input logic clk_i,
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input logic nreset_i,
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input logic [ 7:0] rdata_i,
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input logic [ 7:0] f_i,
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output state_t state_o,
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output logic [15:0] pc_o,
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output logic [15:0] sp_o,
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output logic instr_valid_o,
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output logic instr_undef_o,
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output logic [ 7:0] operand8_o,
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output logic [15:0] operand16_o,
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output logic alu_op_valid_o,
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output alu_op_t alu_op_o,
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output logic reg_write_alu_o,
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output op_src_t op_src_o,
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output op_dest_t op_dest_o,
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output reg8_t reg8_dest_o,
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output reg8_t reg8_src_o,
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output alu16_op_t alu16_op_o,
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output reg16_t reg16_src_o,
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output reg16_t reg16_dest_o,
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output logic memory_we_o,
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output adr_src_t adr_src_o
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);
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logic nreset_r;
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logic halted_r;
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logic state_we;
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state_t state_r;
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state_t state_next;
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logic pc_we;
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logic [15:0] pc_r;
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logic [15:0] pc_next;
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logic sp_we;
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logic [15:0] sp_r;
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logic [15:0] sp_next;
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logic instr_pc_we;
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logic [15:0] instr_pc_r;
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logic [15:0] instr_pc_next;
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logic instr_we;
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logic [ 7:0] instr_r;
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logic [ 7:0] instr_next;
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logic operand0_we;
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logic [ 7:0] operand0_r;
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logic [ 7:0] operand0_next;
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logic operand1_we;
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logic [ 7:0] operand1_r;
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logic [ 7:0] operand1_next;
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logic [ 7:0] decoder_instr0_selected;
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logic [ 7:0] decoder_instr1_selected;
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logic [ 7:0] decoder_instr2_selected;
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logic decoder_need_instr1;
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logic decoder_need_instr2;
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logic decoder_is_multicycle;
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logic decoder_is_undef;
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logic decoder_alu_op_valid;
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logic decoder_memory_we;
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adr_src_t decoder_adr_src;
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logic decoder_sp_we;
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logic is_undef;
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logic pc_incr;
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logic instr_valid;
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logic branch_taken;
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logic branch_cc_true;
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logic branch_always;
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sp_src_t sp_src;
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pc_src_t pc_src;
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cc_t cc;
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always_ff @(posedge clk_i) begin
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nreset_r <= nreset_i;
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end
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always_ff @(posedge clk_i or negedge nreset_i) begin
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if (~nreset_i)
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halted_r <= 1'b0;
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else if (is_undef)
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halted_r <= halted_r | is_undef;
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end
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`DEF_FF(state_r, state_next, state_we, ST0_ADDR);
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`DEF_FF(pc_r, pc_next, pc_we, '0);
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`DEF_FF(sp_r, sp_next, sp_we, '0);
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`DEF_FF(instr_pc_r, instr_pc_next, instr_pc_we, '0);
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`DEF_FF(instr_r, instr_next, instr_we, '0);
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`DEF_FF(operand0_r, operand0_next, operand0_we, '0);
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`DEF_FF(operand1_r, operand1_next, operand1_we, '0);
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assign pc_we = (nreset_r & ~is_undef & ~halted_r) & (pc_incr | branch_taken);
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assign pc_next = (branch_taken & pc_src == PC_SRC_OPERAND8) ? (pc_r + {{8{operand0_r[7]}}, operand0_r}) :
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(branch_taken & pc_src == PC_SRC_OPERAND16) ? {operand1_r, operand0_r} :
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(pc_r + 16'b1);
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assign sp_we = instr_valid & decoder_sp_we;
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assign sp_next = (sp_src == SP_SRC_OPERAND16) ? {operand1_r, operand0_r} :
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(sp_src == SP_SRC_INC) ? (sp_r + 16'h01) :
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(sp_src == SP_SRC_DEC) ? (sp_r + 16'hFFFF) :
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'0;
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assign instr_we = (state_r == ST1_DEC);
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assign instr_next = rdata_i;
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assign instr_pc_we = (state_r == ST0_ADDR);
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assign instr_pc_next = pc_r;
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assign operand0_we = (state_r == ST2_DEC);
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assign operand0_next = rdata_i;
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assign operand1_we = (state_r == ST3_DEC);
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assign operand1_next = rdata_i;
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assign state_we = nreset_r & ~is_undef & ~halted_r;
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always_comb begin
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case (state_r)
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ST0_ADDR: state_next = ST1_DEC;
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ST1_DEC: state_next = decoder_need_instr1 ? ST2_DEC : ST2_EXEC;
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ST2_EXEC: state_next = decoder_is_multicycle ? ST3_EXEC : ST0_ADDR;
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ST2_DEC: state_next = decoder_need_instr2 ? ST3_DEC : ST3_EXEC;
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ST3_DEC: state_next = ST4_EXEC;
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ST3_EXEC: state_next = ST0_ADDR;
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ST4_EXEC: state_next = decoder_is_multicycle ? ST5_EXEC : ST0_ADDR;
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ST5_EXEC: state_next = ST0_ADDR;
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endcase
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end
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decode decode_inst (
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.instr0_i (decoder_instr0_selected),
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.instr1_i (decoder_instr1_selected),
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.instr2_i (decoder_instr2_selected),
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.state_i (state_r),
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.need_instr1_o (decoder_need_instr1),
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.need_instr2_o (decoder_need_instr2),
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.is_multicycle_o(decoder_is_multicycle),
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.undef_o (decoder_is_undef),
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.sp_we_o (decoder_sp_we),
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.sp_src_o (sp_src),
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.alu_op_valid_o(decoder_alu_op_valid),
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.alu_op_o (alu_op_o),
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.reg_write_alu_o(reg_write_alu_o),
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.op_src_o (op_src_o),
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.op_dest_o (op_dest_o),
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.reg8_dest_o (reg8_dest_o),
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.reg8_src_o (reg8_src_o),
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.alu16_op_o (alu16_op_o),
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.reg16_src_o (reg16_src_o),
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.reg16_dest_o (reg16_dest_o),
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.memory_we_o (decoder_memory_we),
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.adr_src_o (decoder_adr_src),
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.branch_always_o(branch_always),
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.cc_o (cc),
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.pc_src_o (pc_src)
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);
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assign decoder_instr0_selected = (state_r == ST1_DEC) ? rdata_i : instr_r;
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assign decoder_instr1_selected = (state_r == ST2_DEC) ? rdata_i : operand0_r;
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assign decoder_instr2_selected = (state_r == ST3_DEC) ? rdata_i : operand1_r;
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assign is_undef = instr_valid & decoder_is_undef;
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assign instr_valid = (state_r == ST2_EXEC | state_r == ST3_EXEC | state_r == ST4_EXEC | state_r == ST5_EXEC);
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assign alu_op_valid_o = decoder_alu_op_valid & instr_valid;
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assign pc_incr = (state_r == ST0_ADDR) | (state_r == ST1_DEC & decoder_need_instr1) | (state_r == ST2_DEC & decoder_need_instr2);
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assign branch_taken = instr_valid & (pc_src != PC_SRC_SEQ) & (branch_cc_true | branch_always);
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assign branch_cc_true = ((cc == CC_NZ) & ~f_i[7]) |
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((cc == CC_Z) & f_i[7]) |
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((cc == CC_NC) & ~f_i[4]) |
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((cc == CC_C) & f_i[4]);
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assign state_o = state_r;
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assign pc_o = pc_r;
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assign sp_o = sp_r;
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assign instr_valid_o = instr_valid;
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assign instr_undef_o = is_undef;
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assign operand8_o = operand0_r;
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assign operand16_o = {operand1_r, operand0_r};
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assign memory_we_o = instr_valid & decoder_memory_we;
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assign adr_src_o = instr_valid ? decoder_adr_src :
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ADR_SRC_PC;
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endmodule : control
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