137 lines
4.2 KiB
Systemverilog
137 lines
4.2 KiB
Systemverilog
`include "cpu_pkg.svh"
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import cpu_pkg::*;
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module cpu (
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input logic clk_i,
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input logic nreset_i,
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output logic [15:0] address_o,
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input logic [ 7:0] rdata_i,
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output logic we_o,
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output logic [ 7:0] wdata_o
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);
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state_t state;
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logic alu_op_valid;
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alu_op_t alu_op;
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op_src_t op_src;
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op_dest_t op_dest;
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adr_src_t adr_src;
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logic reg_write_alu;
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logic [ 7:0] alu_operand;
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logic [ 7:0] rega;
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logic [ 7:0] regf;
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logic [15:0] pc;
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logic [15:0] sp;
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logic [15:0] hl;
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logic instr_valid;
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logic instr_undef;
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logic [ 7:0] operand8;
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logic [15:0] operand16;
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reg8_t reg8_wselect;
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logic reg8_we;
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logic [ 7:0] reg8_wdata;
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reg16_t reg16_wselect;
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logic reg16_we;
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logic [15:0] reg16_wdata;
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reg8_t reg8_rselect;
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reg16_t reg16_rselect;
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reg16_t reg16_rselect2;
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logic [ 7:0] reg8_rdata;
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logic [15:0] reg16_rdata;
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logic [15:0] reg16_rdata2;
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alu16_op_t alu16_op;
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logic [ 7:0] alu_out8;
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logic [15:0] alu_out16;
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control control_inst (
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.clk_i (clk_i),
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.nreset_i (nreset_i),
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.rdata_i (rdata_i),
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.state_o (state),
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.f_i (regf),
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.pc_o (pc),
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.sp_o (sp),
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.alu_op_valid_o(alu_op_valid),
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.alu_op_o (alu_op),
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.reg_write_alu_o(reg_write_alu),
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.op_src_o (op_src),
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.op_dest_o (op_dest),
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.instr_valid_o (instr_valid),
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.instr_undef_o (instr_undef),
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.operand8_o (operand8),
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.operand16_o (operand16),
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.reg8_dest_o (reg8_wselect),
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.reg8_src_o (reg8_rselect),
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.alu16_op_o (alu16_op),
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.reg16_src_o (reg16_rselect),
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.reg16_dest_o (reg16_wselect),
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.memory_we_o (we_o),
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.adr_src_o (adr_src)
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);
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alu alu_inst (
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.clk_i (clk_i),
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.nreset_i (nreset_i),
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.alu_op_valid_i(alu_op_valid),
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.alu_op_i (alu_op),
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.operand_i (alu_operand),
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.inx8_i (operand8[5:3]), // Used for bit/set/res
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.a_o (rega),
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.f_o (regf),
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.alu16_op_i (alu16_op),
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.inx16_i (reg16_rdata2),
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.iny16_i (reg16_rdata),
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.out8_o (alu_out8),
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.out16_o (alu_out16)
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);
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registers registers_inst (
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.clk_i (clk_i),
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.nreset_i(nreset_i),
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.reg8_wselect_i (reg8_wselect),
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.reg8_we_i (reg8_we),
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.reg8_wdata_i (reg8_wdata),
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.reg16_wselect_i(reg16_wselect),
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.reg16_we_i (reg16_we),
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.reg16_wdata_i (reg16_wdata),
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.reg8_rselect_i (reg8_rselect),
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.reg8_rdata_o (reg8_rdata),
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.reg16_rselect_i(reg16_rselect),
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.reg16_rdata_o (reg16_rdata),
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.reg16_rselect2_i(reg16_rselect2),
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.reg16_rdata2_o (reg16_rdata2),
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.hl_o (hl)
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);
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assign alu_operand = (op_src == OP_SRC_A) ? rega :
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(op_src == OP_SRC_OPERAND8) ? operand8 :
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(op_src == OP_SRC_REG8) ? reg8_rdata :
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(op_src == OP_SRC_MEMORY) ? rdata_i :
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'X;
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assign reg8_we = instr_valid & (op_dest == OP_DEST_REG8);
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assign reg8_wdata = reg_write_alu ? alu_out8 : alu_operand;
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assign reg16_we = instr_valid & (op_dest == OP_DEST_REG16);
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assign reg16_wdata = (op_src == OP_SRC_OPERAND16) ? operand16 : alu_out16;
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assign reg16_rselect2 = reg16_wselect;
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assign address_o = (adr_src == ADR_SRC_HL) ? hl :
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(adr_src == ADR_SRC_REG8) ? {8'hFF, reg8_rdata} :
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(adr_src == ADR_SRC_REG16) ? reg16_rdata :
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(adr_src == ADR_SRC_OPERAND16) ? operand16 :
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pc;
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assign wdata_o = (op_dest == OP_DEST_MEMORY) ? alu_operand :
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rega; // ldi/ldd hl, a use the normal control paths for HL
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endmodule : cpu
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