106 lines
2.3 KiB
Systemverilog
106 lines
2.3 KiB
Systemverilog
package cpu_pkg;
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//
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// 4 | ST0_ADDR -> ST1_DEC -> ST2_EXEC -> ST3_NOP
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// 12 | '-> ST2_DEC -> ST3_DEC -> ST4_EXEC -> .... -> ST11_NOP
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//
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typedef enum {
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ST0_ADDR,
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ST1_DEC,
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ST2_EXEC,
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ST2_DEC,
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ST3_DEC,
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ST3_EXEC,
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ST4_EXEC
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} state_t;
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typedef enum logic [2:0] {
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REG8_B = 3'h00,
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REG8_C = 3'h01,
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REG8_D = 3'h02,
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REG8_E = 3'h03,
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REG8_H = 3'h04,
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REG8_L = 3'h05,
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REG8_PHL = 3'h06,
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REG8_A = 3'h07
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} reg8_t;
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typedef enum logic [1:0] {
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REG16_BC = 2'h00,
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REG16_DE = 2'h01,
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REG16_HL = 2'h02,
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REG16_SP_AF = 2'h03
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} reg16_t;
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typedef enum logic [1:0] {
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CC_NZ = 2'h00,
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CC_Z = 2'h01,
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CC_NC = 2'h02,
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CC_C = 2'h03
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} cc_t;
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typedef enum logic [4:0] {
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ALU_OP_ADD = 5'h00,
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ALU_OP_ADC = 5'h01,
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ALU_OP_SUB = 5'h02,
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ALU_OP_SBC = 5'h03,
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ALU_OP_AND = 5'h04,
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ALU_OP_XOR = 5'h05,
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ALU_OP_OR = 5'h06,
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ALU_OP_CP = 5'h07,
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ALU_OP_BIT = 5'h08,
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ALU_OP_NOP = 5'h09,
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ALU_OP_INC = 5'h10,
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ALU_OP_INCR = 5'h11 // Increment register instead of a
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} alu_op_t;
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typedef enum logic [1:0] {
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ALU16_OP_ADD = 2'h00,
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ALU16_INC = 2'h01,
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ALU16_DEC = 2'h02
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} alu16_op_t;
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typedef enum {
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OP_SRC_A,
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OP_SRC_REG8,
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OP_SRC_OPERAND8,
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OP_SRC_MEMORY,
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OP_SRC_OPERAND16,
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OP_SRC_REG16
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} op_src_t;
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typedef enum {
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OP_DEST_A,
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OP_DEST_REG8,
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OP_DEST_REG16,
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OP_DEST_MEMORY
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} op_dest_t;
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typedef enum {
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SP_SRC_OPERAND16
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} sp_src_t;
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typedef enum {
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ADR_SRC_PC,
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ADR_SRC_HL,
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ADR_SRC_REG8, // extended with FF
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ADR_SRC_REG16,
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ADR_SRC_OPERAND16
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} adr_src_t;
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typedef enum {
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PC_SRC_SEQ,
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PC_SRC_OPERAND8
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} pc_src_t;
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endpackage
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`define DEF_FF(register, next, we, rst_value) \
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always_ff @(posedge clk_i or negedge nreset_i) begin \
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if (~nreset_i) begin \
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register <= (rst_value); \
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end else if ((we)) begin \
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register <= (next); \
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end \
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end
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