157 lines
6.5 KiB
Systemverilog
157 lines
6.5 KiB
Systemverilog
`include "cpu_pkg.svh"
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import cpu_pkg::*;
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module decode (
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input logic [7:0] instr0_i,
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input logic [7:0] instr1_i,
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input logic [7:0] instr2_i,
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input state_t state_i,
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output logic need_instr1_o,
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output logic need_instr2_o,
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output logic undef_o,
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output logic sp_we_o,
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output sp_src_t sp_src_o,
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output logic alu_op_valid_o,
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output alu_op_t alu_op_o,
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output logic reg_write_alu_o,
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output op_src_t op_src_o,
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output op_dest_t op_dest_o,
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output reg8_t reg8_dest_o,
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output reg8_t reg8_src_o,
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output alu16_op_t alu16_op_o,
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output reg16_t reg16_dest_o,
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output reg16_t reg16_src_o,
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output cc_t cc_o,
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output pc_src_t pc_src_o,
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output adr_src_t adr_src_o,
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output logic memory_we_o
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);
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logic [1:0] dec_x;
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logic [2:0] dec_y;
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logic [2:0] dec_z;
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logic [1:0] dec_p;
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logic dec_q;
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logic is_cb;
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logic is_ld_r_r;
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logic is_ld_a_nn;
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logic is_ld_r_nn;
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logic is_ldh_c_a;
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logic is_ld_rrrr_a;
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logic is_ld_nnnn_a;
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logic is_ld_rr_nnnn;
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logic is_ld_sp_nnnn;
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logic is_ldd_hl_a;
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logic is_alu_a_r;
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logic is_bit_n_r;
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logic is_inc_a;
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logic is_inc_r;
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logic is_jr_cc_n;
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reg8_t reg8_dest;
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reg8_t reg8_src;
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assign dec_x = instr0_i[7:6];
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assign dec_y = instr0_i[5:3];
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assign dec_z = instr0_i[2:0];
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assign dec_p = instr0_i[5:4];
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assign dec_q = instr0_i[3];
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assign is_cb = (instr0_i == 8'hCB);
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assign is_ld_r_r = (dec_x == 2'h1) & ((dec_z != 3'h6) | (dec_y != 3'h6));
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assign is_ld_a_nn = is_ld_r_nn & (reg8_dest == REG8_A);
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assign is_ld_r_nn = (dec_x == 2'h0) & (dec_z == 3'h6);
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assign is_ld_rr_nnnn = (dec_x == 2'h0) & (dec_z == 3'h1) & ~dec_q & (dec_p != 2'h3);
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assign is_ld_sp_nnnn = (dec_x == 2'h0) & (dec_z == 3'h1) & ~dec_q & (dec_p == 2'h3);
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assign is_ldd_hl_a = (dec_x == 2'h0) & (dec_z == 3'h2) & ~dec_q & (dec_p == 2'h3);
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assign is_ld_rrrr_a = (dec_x == 2'h0) & (dec_z == 3'h2) & ~dec_q & (dec_p != 2'h3);
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assign is_ld_nnnn_a = (dec_x == 2'h0) & (dec_z == 3'h2) & ~dec_q & (dec_p == 2'h2);
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assign is_ldh_c_a = instr0_i == 8'hE2;
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assign is_alu_a_r = (dec_x == 3'h2);
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assign is_bit_n_r = (is_cb & instr1_i[7:6] == 2'h1);
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assign is_inc_a = is_inc_r & (reg8_dest == REG8_A);
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assign is_inc_r = (dec_x == 2'h0) & (dec_z == 3'h4);
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assign is_jr_cc_n = (dec_x == 2'h0) & (dec_z == 2'h0) & dec_y[2];
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assign reg8_src = is_cb ? reg8_t'(instr1_i[2:0]) :
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is_ldh_c_a ? REG8_C :
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is_inc_r ? reg8_t'(dec_y) :
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reg8_t'(dec_z);
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assign reg8_dest = reg8_t'(dec_y);
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assign need_instr1_o = is_ld_sp_nnnn | is_ld_rr_nnnn | is_cb | is_jr_cc_n | is_ld_r_nn;
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assign need_instr2_o = is_ld_sp_nnnn | is_ld_rr_nnnn;
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assign undef_o = ~(is_ld_r_r | is_ld_sp_nnnn | is_ld_rr_nnnn | is_alu_a_r | is_ldd_hl_a | is_bit_n_r | is_jr_cc_n | is_ld_r_nn | is_ldh_c_a | is_inc_r | is_ld_rrrr_a);
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assign sp_we_o = is_ld_sp_nnnn & (state_i == ST4_EXEC);
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assign alu_op_valid_o = is_alu_a_r | is_bit_n_r | is_ld_a_nn | is_inc_r;
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assign alu_op_o = is_bit_n_r ? ALU_OP_BIT :
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is_ld_a_nn ? ALU_OP_NOP :
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is_inc_a ? ALU_OP_INC :
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is_inc_r ? ALU_OP_INCR :
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alu_op_t'({1'b0, dec_y});
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assign reg_write_alu_o = is_inc_r;
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assign op_dest_o = (is_ld_r_r & reg8_dest == REG8_PHL) ? OP_DEST_MEMORY :
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(is_ld_r_nn & reg8_dest == REG8_PHL) ? OP_DEST_MEMORY :
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(is_ld_r_r & reg8_dest == REG8_A) ? OP_DEST_A :
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is_ld_r_r ? OP_DEST_REG8 :
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is_ld_a_nn ? OP_DEST_A :
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is_ld_r_nn ? OP_DEST_REG8 :
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is_ldh_c_a ? OP_DEST_MEMORY :
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is_ld_rr_nnnn ? OP_DEST_REG16 :
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is_ldd_hl_a ? OP_DEST_REG16 :
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is_inc_a ? OP_DEST_A :
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is_inc_r ? OP_DEST_REG8 :
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op_dest_t'('X);
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assign op_src_o = (is_ld_r_r & reg8_src == REG8_A) ? OP_SRC_A :
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(is_alu_a_r & reg8_src == REG8_A) ? OP_SRC_A :
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(is_alu_a_r & reg8_src != REG8_A) ? OP_SRC_REG8 :
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(is_ld_r_r & reg8_src == REG8_PHL) ? OP_SRC_MEMORY :
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is_inc_r ? OP_SRC_REG8 :
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is_ld_r_nn ? OP_SRC_OPERAND8 :
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is_ldh_c_a ? OP_SRC_A :
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is_ld_rr_nnnn ? OP_SRC_OPERAND16 :
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is_ldd_hl_a ? OP_SRC_REG16 :
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is_bit_n_r ? OP_SRC_REG8 :
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op_src_t'('X);
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assign reg8_dest_o = reg8_dest;
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assign reg8_src_o = reg8_src;
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assign reg16_src_o = is_ldd_hl_a ? REG16_HL : reg16_t'(dec_p);
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assign reg16_dest_o = is_ldd_hl_a ? REG16_HL : reg16_t'(dec_p);
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assign pc_src_o = is_jr_cc_n ? PC_SRC_OPERAND8 :
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PC_SRC_SEQ;
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assign adr_src_o = (is_ld_r_r & reg8_dest == REG8_PHL) ? ADR_SRC_HL :
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(is_ld_r_r & reg8_src == REG8_PHL) ? ADR_SRC_HL :
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is_ldd_hl_a ? ADR_SRC_HL :
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(is_ld_r_nn & reg8_dest == REG8_PHL) ? ADR_SRC_HL :
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is_ldh_c_a ? ADR_SRC_REG8 :
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is_ld_nnnn_a ? ADR_SRC_OPERAND16 :
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is_ld_rrrr_a ? ADR_SRC_REG16:
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ADR_SRC_PC;
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assign cc_o = cc_t'(dec_y[1:0]);
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assign memory_we_o = is_ldd_hl_a | is_ldh_c_a | is_ld_rrrr_a | (is_ld_r_nn & reg8_dest == REG8_PHL) | (is_ld_r_r & reg8_dest == REG8_PHL);
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endmodule : decode
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