30 lines
649 B
Systemverilog
30 lines
649 B
Systemverilog
module rom #(
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parameter string FILE_NAME = "",
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parameter integer unsigned ADDR_W = 8,
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parameter integer unsigned DATA_W = 8
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) (
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input logic clk_i,
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input logic cs_i,
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input logic [ADDR_W-1:0] address_i,
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output logic [DATA_W-1:0] rdata_o
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);
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localparam ROM_SIZE = 2**ADDR_W;
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logic [DATA_W-1:0] rom [ROM_SIZE-1:0];
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logic [DATA_W-1:0] rdata;
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always_ff @(posedge clk_i)
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if (cs_i)
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rdata <= rom[address_i];
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assign rdata_o = {DATA_W{cs_i}} & rdata;
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initial begin
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static integer fd = $fopen(FILE_NAME, "rb");
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static integer rv = $fread(rom, fd);
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end
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endmodule : rom
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