105 lines
2.0 KiB
Systemverilog
105 lines
2.0 KiB
Systemverilog
// Top level gb module
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module gb (
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input logic clk,
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input logic nreset,
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// Cartridge bus
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output logic cart_clk_o,
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output logic cart_nreset_o,
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output logic cart_nrd_o,
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output logic cart_nwr_o,
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output logic cart_ncs_o,
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output logic [15:0] cart_addr_o,
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input logic [ 7:0] cart_data_i
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);
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logic [15:0] cpu_addr;
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logic [ 7:0] cpu_rdata;
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logic cpu_we;
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logic [ 7:0] cpu_wdata;
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logic [ 7:0] cpu_ppu_rdata;
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logic rom_enable_r;
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logic rom_sel;
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logic [ 7:0] rom_rdata;
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logic hiram_sel;
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logic hiram_we;
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logic [ 7:0] hiram_rdata;
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logic vram_sel;
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logic vram_we;
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logic [ 7:0] vram_rdata;
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cpu cpu_inst (
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.clk (clk),
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.nreset (nreset),
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.addr_o (cpu_addr),
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.rdata_i(cpu_rdata),
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.we_o (cpu_we),
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.wdata_o(cpu_wdata)
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);
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ppu ppu_inst (
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.clk (clk),
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.nreset (nreset),
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.cpu_addr_i (cpu_addr),
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.cpu_rdata_o(cpu_ppu_rdata),
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.cpu_we_i (cpu_we),
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.cpu_wdata_i(cpu_wdata),
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.cpu_addr_sel_o(ppu_sel)
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);
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assign rom_enable_r = '1;
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assign rom_sel = rom_enable_r & ~(|cpu_addr[15:8]);
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assign vram_sel = (cpu_addr[15:13] == 3'b100);
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assign hiram_sel = (&cpu_addr[15:7]) & ~(&cpu_addr[6:0]);
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assign vram_we = vram_sel & cpu_we;
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assign hiram_we = hiram_sel & cpu_we;
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assign cpu_rdata = ({8{ rom_sel}} & rom_rdata) |
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({8{ vram_sel}} & vram_rdata) |
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({8{hiram_sel}} & hiram_rdata)|
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({8{ ppu_sel}} & cpu_ppu_rdata);
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rom #(
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.FILE_NAME("DMG_ROM.bin"),
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.ADDR_W (8),
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.DATA_W (8)
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) rom_inst (
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.clk (clk),
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.address_i(cpu_addr[7:0]),
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.rdata_o (rom_rdata)
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);
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ram #(
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.ADDR_W (13),
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.DATA_W (8)
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) vram_inst (
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.clk (clk),
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.address_i (cpu_addr[12:0]),
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.rdata_o (vram_rdata),
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.we_i (vram_we),
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.wdata_i (cpu_wdata)
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);
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ram #(
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.ADDR_W (7),
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.DATA_W (8)
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) hiram_inst (
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.clk (clk),
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.address_i (cpu_addr[6:0]),
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.rdata_o (hiram_rdata),
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.we_i (hiram_we),
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.wdata_i (cpu_wdata)
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);
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endmodule : gb |