77 lines
1.7 KiB
Systemverilog
77 lines
1.7 KiB
Systemverilog
module tb_top;
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logic clk;
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logic nreset;
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clkgen clkgen_inst (
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.clk (clk),
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.nreset(nreset)
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);
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gb gb_inst (
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.clk (clk),
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.nreset(nreset)
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);
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logic instr_valid;
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logic instr_undef;
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logic halted;
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logic [15:0] current_pc;
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logic [ 7:0] current_opcode[2:0];
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logic we;
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logic [15:0] last_write_address;
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logic [ 7:0] last_write_value;
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logic vram_sel;
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logic hiram_sel;
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assign halted = gb_inst.cpu_inst.ctrl_inst.halted_r;
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assign instr_valid = gb_inst.cpu_inst.instr_valid;
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assign instr_undef = gb_inst.cpu_inst.ctrl_inst.instr_undef;
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assign current_opcode = gb_inst.cpu_inst.instr;
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assign we = gb_inst.cpu_we;
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assign vram_sel = gb_inst.vram_sel;
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assign hiram_sel = gb_inst.hiram_sel;
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always_ff @(posedge clk or negedge nreset) begin
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if (!nreset)
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current_pc <= '0;
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else if (instr_valid)
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current_pc <= gb_inst.cpu_inst.pc_r;
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end
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always_ff @(posedge clk or negedge nreset) begin
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if (!nreset) begin
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last_write_address <= '0;
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last_write_value <= '0;
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end else if (we) begin
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last_write_address <= gb_inst.cpu_addr;
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last_write_value <= gb_inst.cpu_wdata;
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end
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end
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// SVA code here
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`include "sva_common.svh"
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`SVA_DEF_CLK(clk);
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`SVA_DEF_NRESET(nreset);
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`SVA_ASSERT_PROP_FATAL(undefined_opcode_pushed,
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halted |-> !instr_undef,
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$sformatf("PC: 0x%X | Undefined opcode pushed: 0x%X (0x%X, 0x%X)", current_pc, current_opcode[0], current_opcode[1], current_opcode[2])
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);
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logic selected_memory_implemented;
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assign selected_memory_implemented = hiram_sel | vram_sel;
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`SVA_ASSERT_PROP(write_to_unimplemented_memory,
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we |-> selected_memory_implemented,
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$sformatf("PC: 0x%X | Write to unimplemented memory: 0x%X <= 0x%X",
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current_pc, last_write_address, last_write_value)
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);
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endmodule : tb_top
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