synthflow/vivado/vivado_wrapper.tcl

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if {$argc < 1} {
puts "Usage: <command> $argv0 \[options\] \[sources\]"
exit 1
}
set command [lindex $argv 0]
set top ""
set part ""
set sources ""
set output ""
set i 1
while {$i < $argc} {
switch [lindex $argv $i] {
-top {
incr i
if {$i >= $argc} {
puts "Missing parameter after -top"
exit 2
}
set top [lindex $argv $i]
}
-part {
incr i
if {$i >= $argc} {
puts "Missing parameter after -part"
exit 2
}
set part [lindex $argv $i]
}
-o {
incr i
if {$i >= $argc} {
puts "Missing parameter after -o"
exit 2
}
set output [lindex $argv $i]
}
default {
lappend sources [lindex $argv $i]
}
}
incr i
}
foreach src $sources {
if {[string match "*.sv" $src] || [string match "*.v" $src]} {
read_verilog "$src"
}
if {[string match "*.vhdl" $src]} {
read_vhdl "$src"
}
if {[string match "*.xdc" $src]} {
read_xdc "$src"
}
}
if {[string length $top] <= 0} {
puts "Error: top undefined (define with -top <name>)"
exit 3
}
switch "$command" {
sim {
create_project -in_memory sim
#launch_simulation
}
synth {
if {[string length $part] <= 0} {
puts "Error: part undefined (define with -part <name>)"
exit 4
}
if {[string length $output] <= 0} {
puts "Error: output undefined (define with -o <name>)"
exit 4
}
synth_design -top "$top" -part "$part"
opt_design
place_design
route_design
write_bitstream -force "$output"
}
default {
puts "Unknown command $command"
exit 4
}
}