From 767277e341012aa54acd72d26be9ea2fc921ca0c Mon Sep 17 00:00:00 2001
From: Koray Yanik <fumyuun@gmail.com>
Date: Mon, 15 Feb 2021 21:36:59 +0000
Subject: [PATCH] Add a simple makefile and tcl script for vivado

---
 vivado/Makefile.rules     | 34 +++++++++++++++
 vivado/vivado_wrapper.tcl | 92 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 126 insertions(+)
 create mode 100644 vivado/Makefile.rules
 create mode 100644 vivado/vivado_wrapper.tcl

diff --git a/vivado/Makefile.rules b/vivado/Makefile.rules
new file mode 100644
index 0000000..febdb80
--- /dev/null
+++ b/vivado/Makefile.rules
@@ -0,0 +1,34 @@
+TB ?= tb_top
+
+XVLOG ?= xvlog
+XELAB ?= xelab
+XSIM  ?= xsim
+
+vpath %.sv  $(PATH_SRC)
+vpath %.svh $(PATH_SRC)
+vpath %.sdb xsim.dir/work
+
+.PHONY: all clean sim_build sim sim_gui
+
+all: sim
+
+%.sdb: %.sv
+	$(XVLOG) --sv --nolog $<
+	rm xvlog.pb
+
+xsim.dir/work.$(TB)/xsim.dbg:	$(subst sv,sdb,$(SOURCES))
+	$(XELAB) --nolog --debug all -Odisable_unused_removal $(TB)
+	rm -f xelab.pb
+
+sim_build:	xsim.dir/work.$(TB)/xsim.dbg
+
+sim:	sim_build
+	$(XSIM) --nolog --runall $(TB)
+	rm -f xsim.jou xsim_* webtalk*
+
+sim_gui:	xsim.dir/work.$(TB)/xsim.dbg
+	$(XSIM) --nolog --gui $(TB)
+	rm -f xsim.jou xsim_* webtalk* work.$(TB).wdb vivado_pid*.zip
+
+clean:
+	rm -rf xsim.dir xsim* webtalk* xelab.pb xvlog.pb .Xil
diff --git a/vivado/vivado_wrapper.tcl b/vivado/vivado_wrapper.tcl
new file mode 100644
index 0000000..07e8d47
--- /dev/null
+++ b/vivado/vivado_wrapper.tcl
@@ -0,0 +1,92 @@
+if {$argc < 1} {
+	puts "Usage: <command> $argv0 \[options\] \[sources\]"
+	exit 1
+}
+
+set command [lindex $argv 0]
+
+set top ""
+set part ""
+set sources ""
+set output ""
+
+set i 1
+while {$i < $argc} {
+
+	switch [lindex $argv $i] {
+		-top {
+			incr i
+			if {$i >= $argc} {
+				puts "Missing parameter after -top"
+				exit 2
+			}
+			set top [lindex $argv $i]
+		}
+		-part {
+			incr i
+			if {$i >= $argc} {
+				puts "Missing parameter after -part"
+				exit 2
+			}
+			set part [lindex $argv $i]
+		}
+		-o {
+			incr i
+			if {$i >= $argc} {
+				puts "Missing parameter after -o"
+				exit 2
+			}
+			set output [lindex $argv $i]
+		}
+		default {
+			lappend sources [lindex $argv $i]
+		}
+	}
+
+	incr i
+}
+
+foreach src $sources {
+	if {[string match "*.sv" $src] || [string match "*.v" $src]} {
+		read_verilog "$src"
+	}
+	if {[string match "*.vhdl" $src]} {
+		read_vhdl "$src"
+	}
+	if {[string match "*.xdc" $src]} {
+		read_xdc "$src"
+	}
+}
+
+if {[string length $top] <= 0} {
+	puts "Error: top undefined (define with -top <name>)"
+	exit 3
+}
+
+switch "$command" {
+	sim {
+		create_project -in_memory sim
+		
+		#launch_simulation
+	}
+	synth {
+		if {[string length $part] <= 0} {
+			puts "Error: part undefined (define with -part <name>)"
+			exit 4
+		}
+		if {[string length $output] <= 0} {
+			puts "Error: output undefined (define with -o <name>)"
+			exit 4
+		}
+		synth_design -top "$top" -part "$part"
+		opt_design
+		place_design
+		route_design
+		write_bitstream -force "$output"
+	}
+	default {
+		puts "Unknown command $command"
+		exit 4
+	}
+}
+