30 lines
732 B
Python
30 lines
732 B
Python
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from ReBba.Components.ExiClock import ClockState
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from amaranth import *
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from amaranth.build import Platform
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class ShiftRegister(Elaboratable):
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def __init__(self, width):
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self.width = width
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# Ports
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self.nen = Signal()
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self.exiClkState = Signal(2)
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self.rst = Signal()
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self.inb = Signal()
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self.data = Signal(self.width, reset=0)
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def elaborate(self, platform: Platform):
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m = Module()
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with m.If(self.rst):
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m.d.sync += self.data.eq(self.data.reset)
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with m.If(~self.nen):
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with m.If(self.exiClkState == ClockState.FALLING):
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m.d.sync += self.data.eq(self.data.shift_left(1) | self.inb )
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return m
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