231 lines
8.4 KiB
Python
231 lines
8.4 KiB
Python
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import os
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import subprocess
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from amaranth.build import *
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from amaranth.vendor.xilinx_7series import *
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from .resources import *
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__all__ = ["ArtyA7_35Platform", "ArtyA7_100Platform"]
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class _ArtyA7Platform(Xilinx7SeriesPlatform):
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package = "csg324"
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speed = "1L"
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default_clk = "clk100"
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default_rst = "rst"
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resources = [
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Resource("clk100", 0, Pins("E3", dir="i"),
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Clock(100e6), Attrs(IOSTANDARD="LVCMOS33")),
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Resource("rst", 0, PinsN("C2", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
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*LEDResources(pins="H5 J5 T9 T10", attrs=Attrs(IOSTANDARD="LVCMOS33")),
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RGBLEDResource(0, r="G6", g="F6", b="E1", attrs=Attrs(IOSTANDARD="LVCMOS33")),
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RGBLEDResource(1, r="G3", g="J4", b="G4", attrs=Attrs(IOSTANDARD="LVCMOS33")),
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RGBLEDResource(2, r="J3", g="J2", b="H4", attrs=Attrs(IOSTANDARD="LVCMOS33")),
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RGBLEDResource(3, r="K1", g="H6", b="K2", attrs=Attrs(IOSTANDARD="LVCMOS33")),
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*ButtonResources(pins="D9 C9 B9 B8 ", attrs=Attrs(IOSTANDARD="LVCMOS33")),
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*SwitchResources(pins="A8 C11 C10 A10", attrs=Attrs(IOSTANDARD="LVCMOS33")),
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UARTResource(0,
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rx="A9", tx="D10",
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attrs=Attrs(IOSTANDARD="LVCMOS33")
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),
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SPIResource(0,
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cs_n="C1", clk="F1", copi="H1", cipo="G1",
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attrs=Attrs(IOSTANDARD="LVCMOS33")
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),
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Resource("i2c", 0,
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Subsignal("scl", Pins("L18", dir="io")),
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Subsignal("sda", Pins("M18", dir="io")),
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Subsignal("scl_pullup", Pins("A14", dir="o")),
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Subsignal("sda_pullup", Pins("A13", dir="o")),
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Attrs(IOSTANDARD="LVCMOS33")
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),
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*SPIFlashResources(0,
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cs_n="L13", clk="L16", copi="K17", cipo="K18", wp_n="L14", hold_n="M14",
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attrs=Attrs(IOSTANDARD="LVCMOS33")
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),
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Resource("ddr3", 0,
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Subsignal("rst", PinsN("K6", dir="o")),
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Subsignal("clk", DiffPairs("U9", "V9", dir="o"), Attrs(IOSTANDARD="DIFF_SSTL135")),
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Subsignal("clk_en", Pins("N5", dir="o")),
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Subsignal("cs", PinsN("U8", dir="o")),
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Subsignal("we", PinsN("P5", dir="o")),
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Subsignal("ras", PinsN("P3", dir="o")),
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Subsignal("cas", PinsN("M4", dir="o")),
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Subsignal("a", Pins("R2 M6 N4 T1 N6 R7 V6 U7 R8 V7 R6 U6 T6 T8", dir="o")),
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Subsignal("ba", Pins("R1 P4 P2", dir="o")),
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Subsignal("dqs", DiffPairs("N2 U2", "N1 V2", dir="io"),
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Attrs(IOSTANDARD="DIFF_SSTL135")),
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Subsignal("dq", Pins("K5 L3 K3 L6 M3 M1 L4 M2 V4 T5 U4 V5 V1 T3 U3 R3", dir="io"),
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Attrs(IN_TERM="UNTUNED_SPLIT_40")),
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Subsignal("dm", Pins("L1 U1", dir="o")),
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Subsignal("odt", Pins("R5", dir="o")),
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Attrs(IOSTANDARD="SSTL135", SLEW="FAST"),
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),
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Resource("eth_clk25", 0, Pins("G18", dir="o"),
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Clock(25e6), Attrs(IOSTANDARD="LVCMOS33")),
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Resource("eth_clk50", 0, Pins("G18", dir="o"),
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Clock(50e6), Attrs(IOSTANDARD="LVCMOS33")),
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Resource("eth_mii", 0,
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Subsignal("rst", PinsN("C16", dir="o")),
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Subsignal("mdio", Pins("K13", dir="io")),
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Subsignal("mdc", Pins("F16", dir="o")),
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Subsignal("tx_clk", Pins("H16", dir="i")),
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Subsignal("tx_en", Pins("H15", dir="o")),
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Subsignal("tx_data", Pins("H14 J14 J13 H17", dir="o")),
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Subsignal("rx_clk", Pins("F15", dir="i")),
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Subsignal("rx_dv", Pins("G16", dir="i"), Attrs(PULLDOWN="TRUE")), # strap to select MII
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Subsignal("rx_er", Pins("C17", dir="i")),
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Subsignal("rx_data", Pins("D18 E17 E18 G17", dir="i")),
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Subsignal("col", Pins("D17", dir="i")),
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Subsignal("crs", Pins("G14", dir="i")),
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Attrs(IOSTANDARD="LVCMOS33")
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),
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Resource("eth_rmii", 0,
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Subsignal("rst", PinsN("C16", dir="o")),
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Subsignal("mdio", Pins("K13", dir="io")),
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Subsignal("mdc", Pins("F16", dir="o")),
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Subsignal("tx_en", Pins("H15", dir="o")),
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Subsignal("tx_data", Pins("H14 J14", dir="o")),
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Subsignal("rx_crs_dv", Pins("G14", dir="i")),
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Subsignal("rx_dv", Pins("G16", dir="i"), Attrs(PULLUP="TRUE")), # strap to select RMII
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Subsignal("rx_er", Pins("C17", dir="i")),
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Subsignal("rx_data", Pins("D18 E17", dir="i")),
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Attrs(IOSTANDARD="LVCMOS33")
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)
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]
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connectors = [
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Connector("pmod", 0, "G13 B11 A11 D12 - - D13 B18 A18 K16 - -"), # JA
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Connector("pmod", 1, "E15 E16 D15 C15 - - J17 J18 K15 J15 - -"), # JB
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Connector("pmod", 2, "U12 V12 V10 V11 - - U14 V14 T13 U13 - -"), # JC
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Connector("pmod", 3, " D4 D3 F4 F3 - - E2 D2 H2 G2 - -"), # JD
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Connector("ck_io", 0, {
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# Outer Digital Header
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"io0": "V15",
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"io1": "U16",
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"io2": "P14",
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"io3": "T11",
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"io4": "R12",
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"io5": "T14",
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"io6": "T15",
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"io7": "T16",
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"io8": "N15",
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"io9": "M16",
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"io10": "V17",
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"io11": "U18",
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"io12": "R17",
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"io13": "P17",
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# Inner Digital Header
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"io26": "U11",
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"io27": "V16",
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"io28": "M13",
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"io29": "R10",
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"io30": "R11",
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"io31": "R13",
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"io32": "R15",
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"io33": "P15",
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"io34": "R16",
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"io35": "N16",
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"io36": "N14",
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"io37": "U17",
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"io38": "T18",
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"io39": "R18",
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"io40": "P18",
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"io41": "N17",
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# Outer Analog Header as Digital IO
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"a0": "F5",
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"a1": "D8",
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"a2": "C7",
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"a3": "E7",
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"a4": "D7",
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"a5": "D5",
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# Inner Analog Header as Digital IO
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"io20": "B7",
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"io21": "B6",
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"io22": "E6",
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"io23": "E5",
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"io24": "A4",
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"io25": "A3"
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}),
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Connector("xadc", 0, {
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# Outer Analog Header
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"vaux4_n": "C5",
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"vaux4_p": "C6",
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"vaux5_n": "A5",
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"vaux5_p": "A6",
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"vaux6_n": "B4",
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"vaux6_p": "C4",
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"vaux7_n": "A1",
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"vaux7_p": "B1",
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"vaux15_n": "B2",
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"vaux15_p": "B3",
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"vaux0_n": "C14",
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"vaux0_p": "D14",
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# Inner Analog Header
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"vaux12_n": "B7",
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"vaux12_p": "B6",
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"vaux13_n": "E6",
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"vaux13_p": "E5",
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"vaux14_n": "A4",
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"vaux14_p": "A3",
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# Power Measurements
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"vsnsuv_n": "B17",
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"vsnsuv_p": "B16",
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"vsns5v0_n": "B12",
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"vsns5v0_p": "C12",
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"isns5v0_n": "F14",
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"isns5v0_n": "F13",
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"isns0v95_n": "A16",
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"isns0v95_n": "A15",
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})
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]
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def toolchain_prepare(self, fragment, name, **kwargs):
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overrides = {
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"script_before_bitstream":
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"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
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"script_after_bitstream":
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"write_cfgmem -force -format bin -interface spix4 -size 16 "
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"-loadbit \"up 0x0 {name}.bit\" -file {name}.bin".format(name=name),
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"add_constraints":
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"""
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set_property INTERNAL_VREF 0.675 [get_iobanks 34]
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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"""
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}
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return super().toolchain_prepare(fragment, name, **overrides, **kwargs)
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def toolchain_program(self, products, name):
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xc3sprog = os.environ.get("XC3SPROG", "xc3sprog")
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with products.extract("{}.bit".format(name)) as bitstream_filename:
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subprocess.run([xc3sprog, "-c", "nexys4", bitstream_filename], check=True)
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class ArtyA7_35Platform(_ArtyA7Platform):
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device = "xc7a35ti"
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class ArtyA7_100Platform(_ArtyA7Platform):
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device = "xc7a100ti"
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if __name__ == "__main__":
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from .test.blinky import *
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ArtyA7_35Platform().build(Blinky(), do_program=True)
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