re-bba-rb/re-bba/ShiftRegister/ShiftRegister.py

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import enum
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import sys
import os
from amaranth import *
from amaranth.back import verilog
from amaranth.sim import Simulator
#####
# Hardware Description.
#####
class ClockState(enum.Enum):
LOW = 0
FALLING = 1
HIGH = 2
RISING = 3
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class ShiftRegister(Elaboratable):
def __init__(self, width):
self.width = width
# Ports
self.nen = Signal()
self.rst = Signal()
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self.inb = Signal()
self.exiClk = Signal()
self.data = Signal(self.width, reset=0)
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# State
self.prevExiClkValid = Signal()
self.prevExiClk = Signal()
self.prevExiClkState = Signal(2)
self.exiClkState = Signal(2)
def elaborate(self, platform):
m = Module()
with m.If(self.rst):
m.d.sync += self.data.eq(self.data.reset)
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with m.If(~self.nen):
with m.If(self.prevExiClkValid):
m.d.sync += self.prevExiClkState.eq(self.exiClkState)
with m.If(self.prevExiClk ^ self.exiClk):
m.d.sync += self.exiClkState.eq(Cat(self.exiClk, 1))
with m.Else():
m.d.sync += self.exiClkState.eq(Cat(self.exiClk, 0))
with m.If((self.exiClkState == ClockState.FALLING).bool() & (self.exiClkState != self.prevExiClkState).bool()):
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m.d.sync += self.data.eq(self.data.shift_left(1) | self.inb )
m.d.sync += self.prevExiClkValid.eq(1)
m.d.sync += self.prevExiClk.eq(self.exiClk)
with m.Else():
m.d.sync += self.prevExiClkValid.eq(0)
return m
#####
# TestBench
#####
class TestBench:
def __init__(self):
pass
def simExiClock(self, dut):
yield dut.exiClk.eq(~dut.exiClk)
def enabled_test(self):
dut = self.dut
# Disabled ShiftRegister should not Change.
yield dut.nen.eq(1)
for _ in range(10):
yield dut.inb.eq(~dut.inb)
yield from self.simExiClock(dut)
yield from self.simExiClock(dut)
assert not (yield dut.data)
yield
yield
yield
yield from self.simExiClock(dut)
yield from self.simExiClock(dut)
assert not (yield dut.data)
yield
yield
yield
def normal_operation(self):
dut = self.dut
def oracle(i):
if i == 0: return 0x01
if i == 1: return 0x02
if i == 2: return 0x05
if i == 3: return 0x0A
if i == 4: return 0x15
if i == 5: return 0x2A
if i == 6: return 0x55
if i == 7: return 0xAA
if i == 8: return 0x55
if i == 9: return 0xAA
yield dut.nen.eq(0)
for i in range(10):
yield dut.inb.eq(~dut.inb)
yield from self.simExiClock(dut)
yield
yield
yield from self.simExiClock(dut)
yield
yield
assert (yield dut.data) == oracle(i)
def simulate(self):
self.dut = ShiftRegister(8)
sim = Simulator(self.dut)
sim.add_clock(1e-6) # 1 MHz
sim.add_sync_process(self.enabled_test)
with sim.write_vcd(os.path.dirname(os.path.abspath(__file__)) + "/ShiftRegister_enable.vcd"):
sim.run()
self.dut = ShiftRegister(8)
sim = Simulator(self.dut)
sim.add_clock(1e-6) # 1 MHz
sim.add_sync_process(self.normal_operation)
with sim.write_vcd(os.path.dirname(os.path.abspath(__file__)) + "/ShiftRegister_shift.vcd"):
sim.run()
def main():
if(len(sys.argv) == 2):
if sys.argv[1] == "s":
bench = TestBench()
bench.simulate()
if sys.argv[1] == "v":
mod = ShiftRegister(8)
with open(os.path.dirname(os.path.abspath(__file__)) + "/shift_register.v", "w") as f:
f.write(verilog.convert(mod, ports=[mod.exiClk, mod.inb, mod.data]))
else:
bench = TestBench()
bench.simulate()
#####
# Main portion
#####
if __name__ == "__main__":
main()