236 lines
9.2 KiB
Python
236 lines
9.2 KiB
Python
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import os
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import textwrap
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import subprocess
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from amaranth.build import *
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from amaranth.vendor.xilinx_7series import *
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from .resources import *
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__all__ = ["ArtyS7_25Platform", "ArtyS7_50Platform"]
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class _ArtyS7Platform(Xilinx7SeriesPlatform):
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package = "csga324"
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speed = "1"
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default_clk = "clk100"
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default_rst = "rst"
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resources = [
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Resource("clk100", 0, Pins("R2", dir="i"),
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Clock(100e6), Attrs(IOSTANDARD="SSTL135")),
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Resource("rst", 0, PinsN("C18", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
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*LEDResources(pins="E18 F13 E13 H15", attrs=Attrs(IOSTANDARD="LVCMOS33")),
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RGBLEDResource(0, r="J15", g="G17", b="F15", attrs=Attrs(IOSTANDARD="LVCMOS33")),
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RGBLEDResource(1, r="E15", g="F18", b="E14", attrs=Attrs(IOSTANDARD="LVCMOS33")),
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*ButtonResources(pins="G15 K16 J16 H13", attrs=Attrs(IOSTANDARD="LVCMOS33")),
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*SwitchResources(pins="H14 H18 G18 M5", attrs=Attrs(IOSTANDARD="LVCMOS33")),
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UARTResource(0,
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rx="V12", tx="R12",
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attrs=Attrs(IOSTANDARD="LVCMOS33")
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),
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SPIResource(0,
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cs_n="H16", clk="G16", copi="H17", cipo="K14",
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attrs=Attrs(IOSTANDARD="LVCMOS33")
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),
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I2CResource(0,
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scl="J14", sda="J13",
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attrs=Attrs(IOSTANDARD="LVCMOS33")
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),
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*SPIFlashResources(0,
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cs_n="M13", clk="D11", copi="K17", cipo="K18", wp_n="L14", hold_n="M15",
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attrs=Attrs(IOSTANDARD="LVCMOS33")
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),
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Resource("ddr3", 0,
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Subsignal("rst", PinsN("J6", dir="o")),
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Subsignal("clk", DiffPairs("R5", "T4", dir="o"), Attrs(IOSTANDARD="DIFF_SSTL135")),
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Subsignal("clk_en", Pins("T2", dir="o")),
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Subsignal("cs", PinsN("R3", dir="o")),
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Subsignal("we", PinsN("P7", dir="o")),
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Subsignal("ras", PinsN("U1", dir="o")),
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Subsignal("cas", PinsN("V3", dir="o")),
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Subsignal("a", Pins("U2 R4 V2 V4 T3 R7 V6 T6 U7 V7 P6 T5 R6 U6", dir="o")),
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Subsignal("ba", Pins("V5 T1 U3", dir="o")),
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Subsignal("dqs", DiffPairs("K1 N3", "L1 N2", dir="io"),
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Attrs(IOSTANDARD="DIFF_SSTL135")),
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Subsignal("dq", Pins("K2 K3 L4 M6 K6 M4 L5 L6 N4 R1 N1 N5 M2 P1 M1 P2", dir="io"),
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Attrs(IN_TERM="UNTUNED_SPLIT_40")),
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Subsignal("dm", Pins("K4 M3", dir="o")),
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Subsignal("odt", Pins("P5", dir="o")),
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Attrs(IOSTANDARD="SSTL135", SLEW="FAST"),
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),
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]
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connectors = [
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Connector("pmod", 0, "L17 L18 M14 N14 - - M16 M17 M18 N18 - -"), # JA
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Connector("pmod", 1, "P17 P18 R18 T18 - - P14 P15 N15 P16 - -"), # JB
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Connector("pmod", 2, "U15 V16 U17 U18 - - U16 P13 R13 V14 - -"), # JC
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Connector("pmod", 3, "V15 U12 V13 T12 - - T13 R11 T11 U11 - -"), # JD
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Connector("ck_io", 0, {
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# Outer Digital Header
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"io0": "L13",
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"io1": "N13",
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"io2": "L16",
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"io3": "R14",
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"io4": "T14",
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"io5": "R16",
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"io6": "R17",
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"io7": "V17",
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"io8": "R15",
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"io9": "T15",
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"io10": "H16",
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"io11": "H17",
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"io12": "K14",
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"io13": "G16",
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# Inner Digital Header
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"io26": "U11",
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"io27": "T11",
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"io28": "R11",
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"io29": "T13",
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"io30": "T12",
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"io31": "V13",
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"io32": "U12",
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"io33": "V15",
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"io34": "V14",
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"io35": "R13",
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"io36": "P13",
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"io37": "U16",
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"io38": "U18",
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"io39": "U17",
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"io40": "V16",
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"io41": "U15",
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# Outer Analog Header as Digital IO
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"a0": "G13",
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"a1": "B16",
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"a2": "A16",
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"a3": "C13",
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"a4": "C14",
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"a5": "D18",
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# Inner Analog Header as Digital IO
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"io20": "B14",
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"io21": "A14",
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"io22": "D16",
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"io23": "D17",
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"io24": "D14",
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"io25": "D15"
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}),
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Connector("xadc", 0, {
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# Outer Analog Header
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"vaux0_p": "B13",
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"vaux0_n": "A13",
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"vaux1_p": "B15",
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"vaux1_n": "A15",
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"vaux9_p": "E12",
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"vaux9_n": "D12",
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"vaux2_p": "B17",
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"vaux2_n": "A17",
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"vaux10_p": "C17",
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"vaux10_n": "B18",
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"vaux11_p": "E16",
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"vaux11_n": "E17",
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# Inner Analog Header
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"vaux8_p": "B14",
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"vaux8_n": "A14",
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"vaux3_p": "D16",
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"vaux3_n": "D17",
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})
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]
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def toolchain_prepare(self, fragment, name, **kwargs):
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overrides = {
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"script_before_bitstream":
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"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
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"script_after_bitstream":
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"write_cfgmem -force -format mcs -interface spix4 -size 16 "
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"-loadbit \"up 0x0 {name}.bit\" -file {name}.mcs".format(name=name),
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"add_constraints":
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"set_property INTERNAL_VREF 0.675 [get_iobanks 34]"
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}
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return super().toolchain_prepare(fragment, name, **overrides, **kwargs)
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def toolchain_program(self, product, name, *, programmer="vivado", flash=True):
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assert programmer in ("vivado", "openocd")
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if programmer == "vivado":
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if flash:
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# It does not appear possible to reset the FPGA via TCL after
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# flash programming.
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with product.extract("{}.bin".format(name)) as bitstream_filename:
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cmd = textwrap.dedent("""
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open_hw_manager
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connect_hw_server
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open_hw_target
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current_hw_device [lindex [get_hw_devices] 0]
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create_hw_cfgmem -hw_device [current_hw_device] s25fl128sxxxxxx0-spi-x1_x2_x4
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set_property PROGRAM.FILES {{{}}} [current_hw_cfgmem]
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set_property PROGRAM.ADDRESS_RANGE {{use_file}} [current_hw_cfgmem]
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set_property PROGRAM.BLANK_CHECK 1 [current_hw_cfgmem]
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set_property PROGRAM.ERASE 1 [current_hw_cfgmem]
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set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]
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set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]
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create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]
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program_hw_devices
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program_hw_cfgmem
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close_hw_manager
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puts "Vivado TCL cannot reset boards. Reset or power-cycle your board now."
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""").format(bitstream_filename).encode("utf-8")
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subprocess.run(["vivado", "-nolog", "-nojournal", "-mode", "tcl"], input=cmd, check=True)
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else:
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with product.extract("{}.bit".format(name)) as bitstream_filename:
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cmd = textwrap.dedent("""
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open_hw_manager
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connect_hw_server
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open_hw_target
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current_hw_device [lindex [get_hw_devices] 0]
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set_property PROGRAM.FILE {{{}}} [current_hw_device]
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program_hw_devices
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close_hw_manager
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""").format(bitstream_filename).encode("utf-8")
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subprocess.run(["vivado", "-nolog", "-nojournal", "-mode", "tcl"], input=cmd, check=True)
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else:
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openocd = os.environ.get("OPENOCD", "openocd")
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# In order, OpenOCD searches these directories for files:
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# * $HOME/.openocd if $HOME exists (*nix)
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# * Path pointed to by $OPENOCD_SCRIPTS if $OPENOCD_SCRIPTS exists
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# * $APPDATA/OpenOCD on Windows
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# Place the bscan_spi_xc7s50.bit proxy bitstream under a directory
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# named "proxy" in one of the above directories so OpenOCD finds it.
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if flash:
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with product.extract("{}.bin".format(name)) as fn:
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subprocess.check_call([openocd, "-f", "board/arty_s7.cfg",
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"-c", """init;
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jtagspi_init 0 [find proxy/bscan_spi_xc7s50.bit];
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jtagspi_program {} 0;
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xc7_program xc7.tap;
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shutdown""".format(fn)])
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else:
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with product.extract("{}.bit".format(name)) as fn:
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subprocess.check_call(["openocd", "-f", "board/arty_s7.cfg",
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"-c", """init;
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pld load 0 {};
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shutdown""".format(fn)])
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class ArtyS7_50Platform(_ArtyS7Platform):
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device = "xc7s50"
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class ArtyS7_25Platform(_ArtyS7Platform):
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device = "xc7s25"
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if __name__ == "__main__":
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from .test.blinky import *
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ArtyS7_25Platform().build(Blinky(), do_program=True)
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