191 lines
9.1 KiB
Python
191 lines
9.1 KiB
Python
from amaranth.build import *
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__all__ = [
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"SPIFlashResources", "SDCardResources",
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"SRAMResource", "SDRAMResource", "NORFlashResources",
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"DDR3Resource",
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]
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def SPIFlashResources(*args, cs_n, clk, copi, cipo, wp_n=None, hold_n=None,
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conn=None, attrs=None):
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resources = []
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io_all = []
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if attrs is not None:
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io_all.append(attrs)
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io_all.append(Subsignal("cs", PinsN(cs_n, dir="o", conn=conn)))
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io_all.append(Subsignal("clk", Pins(clk, dir="o", conn=conn, assert_width=1)))
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io_1x = list(io_all)
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io_1x.append(Subsignal("copi", Pins(copi, dir="o", conn=conn, assert_width=1)))
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io_1x.append(Subsignal("cipo", Pins(cipo, dir="i", conn=conn, assert_width=1)))
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if wp_n is not None and hold_n is not None:
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io_1x.append(Subsignal("wp", PinsN(wp_n, dir="o", conn=conn, assert_width=1)))
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io_1x.append(Subsignal("hold", PinsN(hold_n, dir="o", conn=conn, assert_width=1)))
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resources.append(Resource.family(*args, default_name="spi_flash", ios=io_1x,
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name_suffix="1x"))
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io_2x = list(io_all)
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io_2x.append(Subsignal("dq", Pins(" ".join([copi, cipo]), dir="io", conn=conn,
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assert_width=2)))
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resources.append(Resource.family(*args, default_name="spi_flash", ios=io_2x,
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name_suffix="2x"))
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if wp_n is not None and hold_n is not None:
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io_4x = list(io_all)
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io_4x.append(Subsignal("dq", Pins(" ".join([copi, cipo, wp_n, hold_n]), dir="io", conn=conn,
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assert_width=4)))
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resources.append(Resource.family(*args, default_name="spi_flash", ios=io_4x,
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name_suffix="4x"))
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return resources
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def SDCardResources(*args, clk, cmd, dat0, dat1=None, dat2=None, dat3=None, cd=None, wp_n=None,
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conn=None, attrs=None):
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resources = []
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io_common = []
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if attrs is not None:
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io_common.append(attrs)
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if cd is not None:
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io_common.append(Subsignal("cd", Pins(cd, dir="i", conn=conn, assert_width=1)))
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if wp_n is not None:
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io_common.append(Subsignal("wp", PinsN(wp_n, dir="i", conn=conn, assert_width=1)))
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io_native = list(io_common)
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io_native.append(Subsignal("clk", Pins(clk, dir="o", conn=conn, assert_width=1)))
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io_native.append(Subsignal("cmd", Pins(cmd, dir="o", conn=conn, assert_width=1)))
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io_1bit = list(io_native)
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io_1bit.append(Subsignal("dat", Pins(dat0, dir="io", conn=conn, assert_width=1)))
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if dat3 is not None:
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# DAT3 has a pullup and works as electronic card detect
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io_1bit.append(Subsignal("ecd", Pins(dat3, dir="i", conn=conn, assert_width=1)))
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resources.append(Resource.family(*args, default_name="sd_card", ios=io_1bit,
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name_suffix="1bit"))
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if dat1 is not None and dat2 is not None and dat3 is not None:
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io_4bit = list(io_native)
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io_4bit.append(Subsignal("dat", Pins(" ".join((dat0, dat1, dat2, dat3)), dir="io",
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conn=conn, assert_width=4)))
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resources.append(Resource.family(*args, default_name="sd_card", ios=io_4bit,
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name_suffix="4bit"))
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if dat3 is not None:
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io_spi = list(io_common)
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# DAT3/CS# has a pullup and doubles as electronic card detect
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io_spi.append(Subsignal("cs", PinsN(dat3, dir="io", conn=conn, assert_width=1)))
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io_spi.append(Subsignal("clk", Pins(clk, dir="o", conn=conn, assert_width=1)))
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io_spi.append(Subsignal("copi", Pins(cmd, dir="o", conn=conn, assert_width=1)))
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io_spi.append(Subsignal("cipo", Pins(dat0, dir="i", conn=conn, assert_width=1)))
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resources.append(Resource.family(*args, default_name="sd_card", ios=io_spi,
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name_suffix="spi"))
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return resources
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def SRAMResource(*args, cs_n, oe_n=None, we_n, a, d, dm_n=None,
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conn=None, attrs=None):
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io = []
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io.append(Subsignal("cs", PinsN(cs_n, dir="o", conn=conn, assert_width=1)))
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if oe_n is not None:
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# Asserted WE# deactivates the D output buffers, so WE# can be used to replace OE#.
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io.append(Subsignal("oe", PinsN(oe_n, dir="o", conn=conn, assert_width=1)))
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io.append(Subsignal("we", PinsN(we_n, dir="o", conn=conn, assert_width=1)))
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io.append(Subsignal("a", Pins(a, dir="o", conn=conn)))
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io.append(Subsignal("d", Pins(d, dir="io", conn=conn)))
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if dm_n is not None:
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io.append(Subsignal("dm", PinsN(dm_n, dir="o", conn=conn))) # dm="LB# UB#"
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if attrs is not None:
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io.append(attrs)
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return Resource.family(*args, default_name="sram", ios=io)
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def SDRAMResource(*args, clk, cke=None, cs_n=None, we_n, ras_n, cas_n, ba, a, dq, dqm=None,
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conn=None, attrs=None):
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io = []
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io.append(Subsignal("clk", Pins(clk, dir="o", conn=conn, assert_width=1)))
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if cke is not None:
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io.append(Subsignal("clk_en", Pins(cke, dir="o", conn=conn, assert_width=1)))
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if cs_n is not None:
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io.append(Subsignal("cs", PinsN(cs_n, dir="o", conn=conn, assert_width=1)))
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io.append(Subsignal("we", PinsN(we_n, dir="o", conn=conn, assert_width=1)))
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io.append(Subsignal("ras", PinsN(ras_n, dir="o", conn=conn, assert_width=1)))
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io.append(Subsignal("cas", PinsN(cas_n, dir="o", conn=conn, assert_width=1)))
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io.append(Subsignal("ba", Pins(ba, dir="o", conn=conn)))
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io.append(Subsignal("a", Pins(a, dir="o", conn=conn)))
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io.append(Subsignal("dq", Pins(dq, dir="io", conn=conn)))
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if dqm is not None:
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io.append(Subsignal("dqm", Pins(dqm, dir="o", conn=conn))) # dqm="LDQM# UDQM#"
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if attrs is not None:
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io.append(attrs)
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return Resource.family(*args, default_name="sdram", ios=io)
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def NORFlashResources(*args, rst=None, byte_n=None, cs_n, oe_n, we_n, wp_n, by, a, dq,
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conn=None, attrs=None):
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resources = []
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io_common = []
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if rst is not None:
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io_common.append(Subsignal("rst", Pins(rst, dir="o", conn=conn, assert_width=1)))
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io_common.append(Subsignal("cs", PinsN(cs_n, dir="o", conn=conn, assert_width=1)))
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io_common.append(Subsignal("oe", PinsN(oe_n, dir="o", conn=conn, assert_width=1)))
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io_common.append(Subsignal("we", PinsN(we_n, dir="o", conn=conn, assert_width=1)))
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io_common.append(Subsignal("wp", PinsN(wp_n, dir="o", conn=conn, assert_width=1)))
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io_common.append(Subsignal("rdy", Pins(by, dir="i", conn=conn, assert_width=1)))
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if byte_n is None:
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io_8bit = list(io_common)
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io_8bit.append(Subsignal("a", Pins(a, dir="o", conn=conn)))
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io_8bit.append(Subsignal("dq", Pins(dq, dir="io", conn=conn, assert_width=8)))
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resources.append(Resource.family(*args, default_name="nor_flash", ios=io_8bit,
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name_suffix="8bit"))
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else:
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*dq_0_14, dq15_am1 = dq.split()
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# If present in a requested resource, this pin needs to be strapped correctly.
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io_common.append(Subsignal("byte", PinsN(byte_n, dir="o", conn=conn, assert_width=1)))
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io_8bit = list(io_common)
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io_8bit.append(Subsignal("a", Pins(" ".join((dq15_am1, a)), dir="o", conn=conn)))
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io_8bit.append(Subsignal("dq", Pins(" ".join(dq_0_14[:8]), dir="io", conn=conn,
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assert_width=8)))
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resources.append(Resource.family(*args, default_name="nor_flash", ios=io_8bit,
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name_suffix="8bit"))
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io_16bit = list(io_common)
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io_16bit.append(Subsignal("a", Pins(a, dir="o", conn=conn)))
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io_16bit.append(Subsignal("dq", Pins(dq, dir="io", conn=conn, assert_width=16)))
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resources.append(Resource.family(*args, default_name="nor_flash", ios=io_16bit,
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name_suffix="16bit"))
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return resources
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def DDR3Resource(*args, rst_n=None, clk_p, clk_n, clk_en, cs_n, we_n, ras_n, cas_n, a, ba, dqs_p, dqs_n, dq, dm, odt,
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conn=None, diff_attrs=None, attrs=None):
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ios = []
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ios.append(Subsignal("rst", PinsN(rst_n, dir="o", conn=conn, assert_width=1)))
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ios.append(Subsignal("clk", DiffPairs(clk_p, clk_n, dir="o", conn=conn, assert_width=1), diff_attrs))
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ios.append(Subsignal("clk_en", Pins(clk_en, dir="o", conn=conn, assert_width=1)))
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ios.append(Subsignal("cs", PinsN(cs_n, dir="o", conn=conn, assert_width=1)))
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ios.append(Subsignal("we", PinsN(we_n, dir="o", conn=conn, assert_width=1)))
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ios.append(Subsignal("ras", PinsN(ras_n, dir="o", conn=conn, assert_width=1)))
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ios.append(Subsignal("cas", PinsN(cas_n, dir="o", conn=conn, assert_width=1)))
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ios.append(Subsignal("a", Pins(a, dir="o", conn=conn)))
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ios.append(Subsignal("ba", Pins(ba, dir="o", conn=conn)))
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ios.append(Subsignal("dqs", DiffPairs(dqs_p, dqs_n, dir="io", conn=conn), diff_attrs))
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ios.append(Subsignal("dq", Pins(dq, dir="io", conn=conn)))
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ios.append(Subsignal("dm", Pins(dm, dir="o", conn=conn)))
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ios.append(Subsignal("odt", Pins(odt, dir="o", conn=conn, assert_width=1)))
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if attrs is not None:
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ios.append(attrs)
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return Resource.family(*args, default_name="ddr3", ios=ios)
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