127 lines
4.3 KiB
Python
127 lines
4.3 KiB
Python
import os
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import subprocess
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from amaranth.build import *
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from amaranth.vendor.intel import *
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from .resources import *
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__all__ = ["RZEasyFPGAA2_2Platform"]
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class RZEasyFPGAA2_2Platform(IntelPlatform):
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device = "EP4CE6" # Cyclone IV 6K LEs
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package = "E22" # EQFP 144 pins
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speed = "C8"
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default_clk = "clk50" # 50MHz builtin clock
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default_rst = "rst"
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resources = [
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# Clock
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Resource("clk50", 0, Pins("23", dir="i"),
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Clock(50e6), Attrs(io_standard="3.3-V LVTTL")),
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# Reset switch, located on the lower left of the board.
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Resource("rst", 0, PinsN("25", dir="i"), Attrs(io_standard="3.3-V LVTTL")),
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# LEDs, located on the bottom of the board.
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*LEDResources(
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pins="87 86 85 84", invert=True,
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attrs=Attrs(io_standard="3.3-V LVTTL")),
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# Buttons, located on the bottom of the board, right of the LEDs.
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*ButtonResources(
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pins="88 89 90 91", invert=True,
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attrs=Attrs(io_standard="3.3-V LVTTL")),
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# Connections to the SKHynix RAM chip on board.
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SDRAMResource(0,
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clk="43", cs_n="72", we_n="69", ras_n="71", cas_n="70",
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ba="73 74", a="76 77 80 83 68 67 66 65 64 60 75 59",
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dq="28 30 31 32 33 34 38 39 54 53 52 51 50 49 46 44",
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dqm="42 55", attrs=Attrs(io_standard="3.3-V LVCMOS")),
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# VGA connector, located on the right of the board.
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VGAResource(0,
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r="106", g="105", b="104",
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hs="101", vs="103"),
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# 4 digit 7 segment display, located on top of the board.
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Display7SegResource(0,
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a="128", b="121", c="125", d="129", e="132", f="126", g="124", dp="127",
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invert=True),
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Resource("display_7seg_ctrl", 0,
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Subsignal("en", Pins("133 135 136 137", dir="o", invert=True)),
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),
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# PS2 port, located on upper right of the board.
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PS2Resource(0, clk="119", dat="120"),
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# LM75 temperature sensor
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I2CResource(0, scl="112", sda="113"),
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# AT24C08 EEPROM
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I2CResource(1, scl="99" , sda="98" ),
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# Buzzer
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Resource("buzzer", 0, PinsN("110", dir="o")),
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# Serial port, located above the VGA port.
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UARTResource(0, tx="114", rx="115"),
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# LCD connector, located above the 7 segment display.
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Resource("lcd_hd44780", 0,
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Subsignal("rs", Pins("141", dir="o")),
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Subsignal("rw", Pins("138", dir="o")),
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Subsignal("e" , Pins("143", dir="o")),
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Subsignal("d" , Pins("142 1 144 3 2 10 7 11", dir="io")),
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),
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# IR receiver, located right of the buttons.
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Resource("cir", 0,
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Subsignal("rx", Pins("100", dir="i"))
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),
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]
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connectors = [
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# Located above the chip.
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Connector("gpio", 0,
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"- - 11 7 2 144 142 138 136 133 129 127 125 121 119 114 112 110 - "
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"- - 24 10 3 1 143 141 137 135 132 128 126 124 120 115 113 111 - "),
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# Located right of the chip.
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Connector("gpio", 1,
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"- - "
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"106 105"
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"104 103"
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"101 100"
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"99 98 "
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"91 90 "
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"89 88 "
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"87 86 "
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"85 84 "
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"- - "),
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# Located below the chip.
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Connector("gpio", 2,
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"30 32 34 39 43 46 50 52 54 58 60 65 67 71 73 75 77 83 - - - "
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"28 31 33 38 42 44 51 53 55 59 64 66 68 70 72 74 76 80 - - - "),
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]
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def toolchain_prepare(self, fragment, name, **kwargs):
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overrides = {
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"add_settings":
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'''set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"'''
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}
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return super().toolchain_prepare(fragment, name, **overrides, **kwargs)
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def toolchain_program(self, products, name):
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quartus_pgm = os.environ.get("QUARTUS_PGM", "quartus_pgm")
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with products.extract("{}.sof".format(name)) as bitstream_filename:
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subprocess.check_call([quartus_pgm, "--haltcc", "--mode", "JTAG",
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"--operation", "P;" + bitstream_filename])
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if __name__ == "__main__":
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from .test.blinky import Blinky
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RZEasyFPGAA2_2Platform().build(Blinky(), do_program=True)
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