184 lines
7.6 KiB
Python
184 lines
7.6 KiB
Python
import os
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import subprocess
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from amaranth.build import *
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from amaranth.vendor.xilinx_7series import *
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from .resources import *
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__all__ = ["Nexys4DDRPlatform"]
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class Nexys4DDRPlatform(Xilinx7SeriesPlatform):
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device = "xc7a100t"
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package = "csg324"
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speed = "1"
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default_clk = "clk100"
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default_rst = "rst"
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resources = [
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Resource("clk100", 0,
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Pins("E3", dir="i"), Clock(100e6), Attrs(IOSTANDARD="LVCMOS33")),
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Resource("rst", 0,
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PinsN("C12", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
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*SwitchResources(
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pins={0: 'J15', 1: 'L16', 2: 'M13', 3: 'R15', 4: 'R17', 5: 'T18',
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6: 'U18', 7: 'R13', 10: 'R16', 11: 'T13', 12: 'H6',
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13: 'U12', 14: 'U11', 15: 'V10'},
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attrs=Attrs(IOSTANDARD="LVCMOS33")),
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*SwitchResources(
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pins={8: 'T8', 9: 'U8'},
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attrs=Attrs(IOSTANDARD="LVCMOS18")),
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*LEDResources(
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pins="H17 K15 J13 N14 R18 V17 U17 U16 V16 T15 U14 T16 V15 V14 V12 V11",
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attrs=Attrs(IOSTANDARD="LVCMOS33")),
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RGBLEDResource(0,
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r="N15", g="M16", b="R12",
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attrs=Attrs(IOSTANDARD="LVCMOS33")),
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RGBLEDResource(1,
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r="N16", g="R11", b="G14",
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attrs=Attrs(IOSTANDARD="LVCMOS33")),
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Display7SegResource(0,
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a="T10", b="R10", c="K16", d="K13", e="P15",
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f="T11", g="L18", dp="H15", invert=True,
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attrs=Attrs(IOSTANDARD="LVCMOS33")),
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Resource("display_7seg_an", 0,
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PinsN("J17 J18 T9 J14 P14 T14 K2 U13", dir="o"),
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Attrs(IOSTANDARD="LVCMOS33")),
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Resource("button_reset", 0,
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PinsN("C12", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
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Resource("button_center", 0,
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Pins("N17", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
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Resource("button_up", 0,
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Pins("M18", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
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Resource("button_left", 0,
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Pins("P17", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
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Resource("button_right", 0,
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Pins("M17", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
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Resource("button_down", 0,
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Pins("P18", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
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VGAResource(0,
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r="A3 B4 C5 A4",
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g="C6 A5 B6 A6",
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b="B7 C7 D7 D8",
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hs="B11", vs="B12",
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attrs=Attrs(IOSTANDARD="LVCMOS33")),
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*SDCardResources(0,
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clk="B1", cmd="C1", cd="A1",
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dat0="C2", dat1="E1", dat2="F1", dat3="D2",
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attrs=Attrs(IOSTANDARD="LVCMOS33")),
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Resource("sd_card_reset", 0,
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Pins("E2", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
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Resource("accelerometer", 0, # ADXL362
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Subsignal("cs", PinsN("D15", dir="o")),
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Subsignal("clk", Pins("F15", dir="o")),
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Subsignal("copi", Pins("F14", dir="o")),
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Subsignal("cipo", Pins("E15", dir="i")),
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Subsignal("int", Pins("B13 C16", dir="i"),
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Attrs(IOSTANDARD="LVCMOS33", PULLUP="TRUE")),
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Attrs(IOSTANDARD="LVCMOS33")),
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Resource("temp_sensor", 0, # ADT7420
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Subsignal("scl", Pins("C14", dir="o")),
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Subsignal("sda", Pins("C15", dir="io")),
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Subsignal("int", Pins("D13", dir="i"), Attrs(PULLUP="TRUE")),
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Subsignal("ct", Pins("B14", dir="i"), Attrs(PULLUP="TRUE")),
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Attrs(IOSTANDARD="LVCMOS33")),
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Resource("microphone", 0, # ADMP421
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Subsignal("clk", Pins("J5", dir="o")),
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Subsignal("data", Pins("H5", dir="i")),
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Subsignal("lr_sel", Pins("F5", dir="o")),
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Attrs(IOSTANDARD="LVCMOS33")),
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Resource("audio", 0,
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Subsignal("pwm", Pins("A11", dir="o")),
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Subsignal("sd", PinsN("D12", dir="o")),
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Attrs(IOSTANDARD="LVCMOS33")),
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UARTResource(0,
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rx="C4", tx="D4", rts="E5", cts="D3",
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attrs=Attrs(IOSTANDARD="LVCMOS33"),
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role="dce"),
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PS2Resource(0,
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clk="F4", dat="B2",
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attrs=Attrs(IOSTANDARD="LVCMOS33", PULLUP="TRUE")),
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Resource("eth", 0, # LAN8720A
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Subsignal("mdio", Pins("A9", dir="io")),
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Subsignal("mdc", Pins("C9", dir="o")),
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Subsignal("reset", Pins("B3", dir="o")),
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Subsignal("rxd", Pins("C11 D10", dir="io")),
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Subsignal("rxerr", Pins("C10", dir="io")),
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Subsignal("txd", Pins("A10 A8", dir="o")),
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Subsignal("txen", Pins("B9", dir="o")),
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Subsignal("crs_dv", Pins("D9", dir="io")),
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Subsignal("int", PinsN("B8", dir="io")),
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Subsignal("clk", Pins("D5", dir="o"), Clock(50e6)),
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Attrs(IOSTANDARD="LVCMOS33")),
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*SPIFlashResources(0,
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cs_n="L13", clk="E9", copi="K17", cipo="K18", wp_n="L14", hold_n="M14",
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attrs=Attrs(IOSTANDARD="LVCMOS33")),
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Resource("ddr2", 0, # MT47H64M16HR-25:H
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Subsignal("a",
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Pins("M4 P4 M6 T1 L3 P5 M2 N1 L4 N5 R2 K5 N6 K3", dir="o")),
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Subsignal("dq",
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Pins("R7 V6 R8 U7 V7 R6 U6 R5 T5 U3 V5 U4 V4 T4 V1 T3", dir="io"),
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Attrs(IN_TERM="UNTUNED_SPLIT_50")),
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Subsignal("ba", Pins("P2 P3 R1", dir="o")),
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Subsignal("clk", DiffPairs("L6", "L5", dir="o"),
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Attrs(IOSTANDARD="DIFF_SSTL18_I")),
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Subsignal("clk_en", Pins("M1", dir="o")),
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Subsignal("cs", PinsN("K6", dir="o")),
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Subsignal("we", PinsN("N2", dir="o")),
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Subsignal("ras", PinsN("N4", dir="o")),
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Subsignal("cas", PinsN("L1", dir="o")),
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Subsignal("dqs", DiffPairs("U9 U2", "V9 V2", dir="o"),
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Attrs(IOSTANDARD="DIFF_SSTL18_I")),
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Subsignal("dm", Pins("T6 U1", dir="o")),
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Subsignal("odt", Pins("R5", dir="o")),
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Attrs(IOSTANDARD="SSTL18_I", SLEW="FAST"))
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]
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connectors = [
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Connector("pmod", 0, "C17 D18 E18 G17 - - D17 E17 F18 G18 - -"), # JA
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Connector("pmod", 1, "D14 F16 G16 H14 - - E16 F13 G13 H16 - -"), # JB
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Connector("pmod", 2, "K1 F6 J2 G6 - - E7 J3 J4 E6 - -"), # JC
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Connector("pmod", 3, "H4 H1 G1 G3 - - H2 G4 G2 F3 - -") # JD
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]
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def toolchain_prepare(self, fragment, name, **kwargs):
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overrides = {
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"script_before_bitstream":
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"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
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"script_after_bitstream":
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"write_cfgmem -force -format bin -interface spix4 -size 16 "
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"-loadbit \"up 0x0 {name}.bit\" -file {name}.bin".format(name=name),
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"add_constraints":
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"""
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set_property INTERNAL_VREF 0.9 [get_iobanks 34]
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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"""
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}
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return super().toolchain_prepare(fragment, name, **overrides, **kwargs)
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def toolchain_program(self, products, name):
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xc3sprog = os.environ.get("XC3SPROG", "xc3sprog")
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with products.extract("{}.bit".format(name)) as bitstream_filename:
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subprocess.run([xc3sprog, "-c", "nexys4", bitstream_filename], check=True)
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if __name__ == "__main__":
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from .test.blinky import *
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Nexys4DDRPlatform().build(Blinky(), do_program=True)
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