160 lines
4.1 KiB
Python
160 lines
4.1 KiB
Python
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import sys
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import os
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from amaranth import *
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from amaranth_boards.icebreaker import *
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from amaranth.back import verilog
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from amaranth.sim import Simulator
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#####
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# Hardware Description.
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#####
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class ShiftRegister(Elaboratable):
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def __init__(self, width):
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self.width = width
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# Ports
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self.nen = Signal()
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self.inb = Signal()
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self.exiClk = Signal()
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# Defines
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self.LOW = 0
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self.FALLING = 1
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self.HIGH = 2
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self.RISING = 3
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# State
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self.data = Signal(self.width)
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self.prevExiClkValid = Signal()
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self.prevExiClk = Signal()
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self.prevExiClkState = Signal(2)
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self.exiClkState = Signal(2)
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def elaborate(self, platform):
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m = Module()
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with m.If(~self.nen):
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with m.If(self.prevExiClkValid):
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m.d.sync += self.prevExiClkState.eq(self.exiClkState)
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with m.If(self.prevExiClk ^ self.exiClk):
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m.d.sync += self.exiClkState.eq(Cat(self.exiClk, 1))
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with m.Else():
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m.d.sync += self.exiClkState.eq(Cat(self.exiClk, 0))
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with m.If((self.exiClkState == self.FALLING).bool() & (self.exiClkState != self.prevExiClkState).bool()):
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m.d.sync += self.data.eq(self.data.shift_left(1) | self.inb )
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m.d.sync += self.prevExiClkValid.eq(1)
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m.d.sync += self.prevExiClk.eq(self.exiClk)
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with m.Else():
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m.d.sync += self.prevExiClkValid.eq(0)
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return m
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#####
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# TestBench
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#####
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class TestBench:
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def __init__(self):
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pass
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def simExiClock(self, dut):
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yield dut.exiClk.eq(~dut.exiClk)
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def enabled_test(self):
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dut = self.dut
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# Disabled ShiftRegister should not Change.
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yield dut.nen.eq(1)
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for _ in range(10):
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yield dut.inb.eq(~dut.inb)
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yield from self.simExiClock(dut)
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yield from self.simExiClock(dut)
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assert not (yield dut.data)
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yield
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yield
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yield
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yield from self.simExiClock(dut)
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yield from self.simExiClock(dut)
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assert not (yield dut.data)
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yield
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yield
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yield
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def normal_operation(self):
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dut = self.dut
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def oracle(i):
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if i == 0: return 0x01
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if i == 1: return 0x02
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if i == 2: return 0x05
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if i == 3: return 0x0A
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if i == 4: return 0x15
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if i == 5: return 0x2A
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if i == 6: return 0x55
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if i == 7: return 0xAA
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if i == 8: return 0x55
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if i == 9: return 0xAA
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yield dut.nen.eq(0)
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for i in range(10):
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yield dut.inb.eq(~dut.inb)
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yield from self.simExiClock(dut)
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yield
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yield
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yield from self.simExiClock(dut)
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yield
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yield
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assert (yield dut.data) == oracle(i)
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def simulate(self):
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self.dut = ShiftRegister(8)
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sim = Simulator(self.dut)
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sim.add_clock(1e-6) # 1 MHz
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sim.add_sync_process(self.enabled_test)
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with sim.write_vcd(os.path.dirname(os.path.abspath(__file__)) + "/ShiftRegister_enable.vcd"):
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sim.run()
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self.dut = ShiftRegister(8)
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sim = Simulator(self.dut)
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sim.add_clock(1e-6) # 1 MHz
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sim.add_sync_process(self.normal_operation)
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with sim.write_vcd(os.path.dirname(os.path.abspath(__file__)) + "/ShiftRegister_shift.vcd"):
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sim.run()
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def main():
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if(len(sys.argv) == 2):
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if sys.argv[1] == "s":
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bench = TestBench()
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bench.simulate()
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if sys.argv[1] == "v":
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mod = ShiftRegister(8)
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with open(os.path.dirname(os.path.abspath(__file__)) + "/shift_register.v", "w") as f:
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f.write(verilog.convert(mod, ports=[mod.exiClk, mod.inb, mod.data]))
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if sys.argv[1] == "p":
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ICEBreakerPlatform().build(ShiftRegister(8), do_program=True)
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else:
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bench = TestBench()
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bench.simulate()
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#####
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# Main portion
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#####
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if __name__ == "__main__":
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main()
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