Clean up hardware repo: kill the resurrecting stale power sheet, restore datasheets
- Remove stale lowercase power.kicad_sch (pre-rework draft; live sheet is
Power.kicad_sch). Both paths were git-tracked, which on a case-insensitive
Windows checkout makes them one file on disk - deleting the stale one also
deleted the live one, and restoring the live sheet resurrected the stale
path at the next commit. Removing the path from the index breaks the loop.
- Remove re-bba-rb.kicad_pcb.old.* leftovers (recoverable from history).
- Restore hardware/re-bba-rb/datasheets/ (deleted accidentally by 3547302)
and add the two missing datasheets: TPS22810 (power) and PUSB3AB6 (exi).
- Add hardware/re-bba-rb/TODO.md capturing the 2026-07-17 review findings
(EXI DO/DI swap, missing W5100S MDI termination, FTDI EEPROM resistors,
iceprog pin mismatch, PR1 margin, BOM/ordering notes); referenced from
CLAUDE.md.
Verified after cleanup: ERC 0 violations, netlist identical (107 components).
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
This commit is contained in:
@@ -253,6 +253,15 @@ reference implementations — use `amaranth.lib.cdc` primitives (`FFSynchronizer
|
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plug (schematic, PCB, custom GameCube symbol library). Used to verify pad geometry
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before ordering the interposer PCB; not part of the FPGA build.
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`hardware/re-bba-rb/` — the actual adapter PCB (FT2232H + iCE40UP5K + W5100S,
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powered from SP1 12 V via buck). **Open findings from the 2026-07-17 hardware
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review live in `hardware/re-bba-rb/TODO.md`** — read it before editing the
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schematics, ordering boards, or writing the board PCF. Highlights: EXI DO/DI are
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swapped vs the (incorrect) SP1 table in `docs/gc_bba_fpga_design.md` (DO = GC→
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adapter = MOSI); the W5100S MDI 49.9 Ω termination network is missing; the FTDI
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EEPROM needs its 2.2 k/10 k resistors; stock iceprog doesn't match the FTDI pin
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mapping.
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---
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## Amaranth Simulator API
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@@ -0,0 +1,156 @@
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# re-bba-rb board — open items from hardware review (2026-07-17)
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Full review of schematics + PCB against component datasheets
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(`datasheets/` — restore from commit `db457a0`, see Housekeeping), the WIZnet
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W5100S reference schematic, and JLCPCB manufacturing limits. ERC/DRC: clean.
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## Critical — must fix before (or with) next fab
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- [ ] **EXI DO/DI swapped at J3** (`exi.kicad_sch`). YAGCD SP1 naming is
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console-perspective: pin 6 `DO` = GC data **out** → adapter's MOSI
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*input*; pin 9 `DI` = GC data **in** ← adapter's MISO *output*. Board has
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J3.6 → EXI_MISO (FPGA output — bus contention with the GC driver) and
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J3.9 → EXI_MOSI. Verified via SD Gecko (MC pin 5 DO → SD CMD input) and
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SD2SP2 (DO → OR gate → SD CMD).
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- [ ] Fix the SP1 pin table in `docs/gc_bba_fpga_design.md` (§ SP1
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pinout, "DO (MISO) Adapter → GC" is backwards — root cause).
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- [ ] Fix schematic labels (or PCB routing) so names match reality.
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- [ ] Decide: keep current copper and swap in `synth.py` pin constraints
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(both FPGA pins are plain IOBs: pin 3 = IOB_9b, pin 4 = IOB_8a),
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or re-route. Existing boards are rescuable in constraints alone.
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- [ ] **W5100S MDI termination network missing** (`ethernet.kicad_sch`).
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Per WIZnet W5100S reference schematic: 49.9 Ω from each of
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TXOP/TXON/RXIP/RXIN to a common node with 0.1 µF to GND, placed near the
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chip ("to avoid the 100M overshoot"); optionally 3.3 Ω series damping in
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each line. Board routes the pairs straight through D4/D5 to the magjack.
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- [ ] Add 4× 49.9 Ω 1% + 2× 0.1 µF termination.
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- [ ] Place C51/C52 physically at J2 pins 4/5 (center taps).
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- [ ] Reconsider D4/D5 (USBLC6 on the line side of the magnetics):
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unusual — transformer already isolates; their VBUS pins float so
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they only clamp to GND. Remove or justify.
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- [ ] **FT2232H EEPROM interface** (`Usb Connector.kicad_sch`): datasheet
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Table 3.4 requires EEDATA → 93LC46B **DO via 2.2 kΩ** plus **10 kΩ
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pull-up on DO to VCC** (DI stays direct). Board ties DO and DI both
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directly to EE_DATA → read contention, unreliable EEPROM enumeration.
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## Functional / robustness
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- [ ] **iceprog pin mismatch**: iceprog hardcodes CS=ADBUS4, CDONE=ADBUS6,
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CRESET=ADBUS7. Board uses FLASH_CS=ADBUS3, CDONE=ACBUS1, CRESET=ACBUS0.
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Rewire to the iCEbreaker convention, or maintain a patched iceprog.
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- [ ] **TPS2116 PR1 divider margin**: 200k/100k gives PR1 = 1.10 V vs
|
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VREF = 1.0 V ±8 % (max 1.08 V) — 20 mV worst-case margin against the
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3.3 V buck output. Change R3 to 150 k → switchover at 2.30–2.70 V.
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- [ ] **ETH_RST pull-up**: W5100S RSTn is a plain input (no internal pull) and
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floats while the FPGA configures. Add 10 k to **ETH_3V3** (not 3V3, so
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it sits low when the ETH rail is off).
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- [ ] **Gateware: gate all outputs on GC_ON** — when GC_ON=0 the W5100S is
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unpowered (U12) and the GC is off, but FPGA banks stay at 3.3 V. Hold
|
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the W5100S bus and EXI outputs Hi-Z/low to avoid back-powering.
|
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- [ ] **Gateware: UART crossover** — net names are FT-perspective
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(UART_TXD = FTDI output = FPGA **RX** on pin 18). Get this right in the
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board PCF.
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- [ ] **Gateware: EXI INT drive style** — prefer open-drain emulation (drive
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low / release) on J3.3 rather than push-pull high.
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## Broader items (beyond the wiring review — block fab on the first two)
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- [ ] **Write the re-bba-rb pin constraints** — `exi_bba/synth.py` still targets
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the iCEbreaker. This board: EXI on FPGA pins 3 (IOB_9b), 4 (IOB_8a),
|
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44 (EXI_CLK, G6), 45 (EXI_CS), 46 (EXI_INT); W5100S bus on the IOT bank
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(23–43); CLK12 on 20 (G3); GC_ON on 21; ETH_RST on 2; UART on 18/19.
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This is where the DO/DI swap and the UART crossover (UART_TXD = FTDI
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output = FPGA RX) get resolved. Pure software; do it before ordering to
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prove the pinout.
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- [ ] **Add debug provisions — the board currently has none.** RGB0–2 are
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unconnected, no LEDs, no button, no test points; the CLAUDE.md bring-up
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plan (StatusPanel heartbeat/activity LEDs + BTN re-init) has nothing to
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drive. Spare IOBs: 6, 9, 10, 11, 12, 13, 47, 48. Add ≥2 LEDs (heartbeat,
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EXI activity), a 4–6 pin debug header (logic-analyzer access — EXI
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CLK/CS/MOSI/MISO are what you probe when enumeration fails), and test
|
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points on 3V3 / 1V2 / ETH_3V3 / GC_ON. Cannot be retrofitted.
|
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- [ ] **Verify mechanical fit** — outline + finger geometry vs SP1ETH/ETH2SP1
|
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references (per CLAUDE.md), RJ45 and USB-C protrusion vs the GC serial
|
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port bay opening. An earlier commit says "need to remeasure PCB outline";
|
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sp1_test_plug validates pads only, not the envelope.
|
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- [x] **SP1 12 V rail viability — VERIFIED against existing projects
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(2026-07-17).** webhdx's IDE-EXI v2 for Serial Port 1 (which became the
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commercial M.2 Loader): "New switching power regulator supplies 3.3V@2A
|
||||
from 12V rail" (webhdx, gc-forever thread t=4843, 2021-08-28) — a
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shipping SP1 product powers an M.2 SATA SSD + RP2040 entirely from
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pin 5's 12 V through a buck, no external supply. That's the same
|
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architecture as this board at several times our load (~130 mA @ 12 V).
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webhdx moved from a linear regulator to a buck because the linear "was
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generating a lot of heat" — validating the TPS562201 choice. The
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official modem (DOL-014) was the original 12 V consumer; SP1ETH leaves
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12 V unused (runs from the 3.3 V pins). Remaining bench check only:
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- [ ] inrush into C65 (100 µF) + 2×10 µF buck input caps at GC power-on
|
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(the M.2 Loader precedent suggests this is a non-issue).
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- [ ] **Decide FT2232H EEPROM contents + flashing workflow** — blank 93LC46B
|
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enumerates with default VID/PID (works, generic); custom
|
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VID/PID/serial/product string needs FT_PROG provisioning. Tied to the
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iceprog-pin-mapping decision above (changes the schematic).
|
||||
- [ ] CC1/CC2 have no ESD protection (USBLC6 covers D+/D− only) — optional,
|
||||
most hobby designs skip; note spare-channel budget if respinning D2 area.
|
||||
- [ ] Ensure `hardware/re-bba-rb/.history/` (contains an embedded `.git`) is
|
||||
gitignored and never committed.
|
||||
|
||||
## Minor / BOM
|
||||
|
||||
- [ ] RSET_BG: datasheet says 12.3 kΩ 1 % (ref schematic: 12 k + 300 Ω);
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board has 12.4 k (~0.8 % off). Match if convenient.
|
||||
- [ ] Crystals Y1 (FTDI 12 MHz) and Y2 (W5100S 25 MHz): 18 pF load caps are
|
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correct **only for CL ≈ 12 pF crystals** — pick parts accordingly
|
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(W5100S Table 9 recommends CL = 12 pF).
|
||||
- [ ] 12 V-rail parts ≥ 25 V rating: C3, C4 (10 µF 0805), C6, C65 (100 µF
|
||||
electrolytic); D3 SMAJ12A already correct.
|
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- [ ] 1 % tolerance required: R1/R2 (buck VFB divider, TI requirement),
|
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R10 (FTDI REF 12 k), R16 (RSET_BG), R3/R4 (PR1 divider).
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- [ ] TPS22810 CT: floating = fastest ramp (~0.7 A inrush into ETH rail
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caps). Consider CT = 10 nF footprint (DNP-able).
|
||||
- [ ] Verify HR911105A internal LED pinout (assumed: 9/12 anodes via
|
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R14/R15 330 Ω to ETH_3V3, 10/11 cathodes to LNKn/ACTn) and the
|
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Bob-Smith common on pin 8 (tied straight to GND here; WIZnet ref
|
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separates chassis via 1 nF/2 kV — acceptable choice, confirm intent).
|
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- [ ] Confirm at bring-up (from CLAUDE.md): W5100S register addresses / MR
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bits were written from memory.
|
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|
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## JLCPCB ordering notes (DRC clean — these are order-form options)
|
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|
||||
- [ ] Stackup = JLC04121H-7628 (matches the 0.2104 mm prepreg / 0.6 mm core,
|
||||
~1.14 mm ≙ JLC nominal 1.2 mm — satisfies the SP1 slot's 1.2 mm spec).
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- [ ] Select **ENIG** (file has copper_finish "None") and **gold fingers +
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45° bevel** for the SP1 edge connector.
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- [ ] Hand-solder / non-economic-assembly parts: C65 (THT electrolytic),
|
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J2 magjack (THT), J1 USB-C, D2 (DFN2111-7, tiny). Plan assembly split.
|
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- [ ] Add LCSC part numbers to symbol fields for JLC PCBA BOM export; check
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fiducials for SMT.
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## Housekeeping (repo) — done 2026-07-17
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- [x] Restored `hardware/re-bba-rb/datasheets/` (deleted by `3547302`) from
|
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the LFS store; added TPS22810 (power/) and PUSB3AB6 (exi/) datasheets
|
||||
that were missing from the original set.
|
||||
- [x] Deleted stale lowercase `power.kicad_sch` (the pre-rework draft from the
|
||||
first power-sheet commit; live sheet is `Power.kicad_sch`). It "kept
|
||||
coming back" because both paths were git-tracked: on a case-insensitive
|
||||
(Windows) checkout they are one file on disk, so deleting one path also
|
||||
deletes the other, and restoring the live sheet re-materialises both —
|
||||
the next commit resurrects the stale path. Removing the lowercase path
|
||||
from the git index (done from the case-sensitive devcontainer) is the
|
||||
permanent fix. **Never add two files differing only in case.**
|
||||
- [x] Deleted `re-bba-rb.kicad_pcb.old.kicad_pcb` / `.old.kicad_pro` leftovers
|
||||
(recoverable from git history if ever needed).
|
||||
|
||||
## Verified correct — do not re-flag
|
||||
|
||||
TPS562201 (EN at 12 V legal, abs max 19 V; 0.768 V ref × 33k/10k = 3.30 V;
|
||||
L/C per Table 7-2) · TPS2116 mode/ST logic (GC priority, USB fallback,
|
||||
GC_ON polarity) · AP2112K ×2 · TPS22810 EN (never floats, R5 pull-up) ·
|
||||
**FT2232H VPHY/VPLL on 3.3 V is correct per datasheet** (the VCORE→3V3
|
||||
relabel at HEAD was a fix) · W5100S parallel-mode straps (MOD=0100, SCLK→GND,
|
||||
pin32=A0/pin33=A1, INTn push-pull, internal pull-ups on CSn/RDn/WRn/DAT) ·
|
||||
W5100S 1V2 loop + mandatory 1 MΩ crystal feedback · PUSB3AB6 pinout/footprint ·
|
||||
USB-C CC/ESD wiring · iCE40 power/config/flash, CLK12 on G3, EXI_CLK on G6 ·
|
||||
magjack transformer spec (1:1, 350 µH) · PCB vs JLCPCB capability floor
|
||||
(rules in `re-bba-rb.kicad_dru`, 0 DRC errors).
|
||||
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@@ -1,753 +0,0 @@
|
||||
{
|
||||
"board": {
|
||||
"3dviewports": [],
|
||||
"design_settings": {
|
||||
"defaults": {
|
||||
"apply_defaults_to_fp_barcodes": false,
|
||||
"apply_defaults_to_fp_dimensions": false,
|
||||
"apply_defaults_to_fp_fields": false,
|
||||
"apply_defaults_to_fp_shapes": false,
|
||||
"apply_defaults_to_fp_text": false,
|
||||
"board_outline_line_width": 0.05,
|
||||
"copper_line_width": 0.2,
|
||||
"copper_text_italic": false,
|
||||
"copper_text_size_h": 1.5,
|
||||
"copper_text_size_v": 1.5,
|
||||
"copper_text_thickness": 0.3,
|
||||
"copper_text_upright": false,
|
||||
"courtyard_line_width": 0.05,
|
||||
"dimension_precision": 4,
|
||||
"dimension_units": 3,
|
||||
"dimensions": {
|
||||
"arrow_length": 1270000,
|
||||
"extension_offset": 500000,
|
||||
"keep_text_aligned": true,
|
||||
"suppress_zeroes": true,
|
||||
"text_position": 0,
|
||||
"units_format": 0
|
||||
},
|
||||
"fab_line_width": 0.1,
|
||||
"fab_text_italic": false,
|
||||
"fab_text_size_h": 1.0,
|
||||
"fab_text_size_v": 1.0,
|
||||
"fab_text_thickness": 0.15,
|
||||
"fab_text_upright": false,
|
||||
"other_line_width": 0.1,
|
||||
"other_text_italic": false,
|
||||
"other_text_size_h": 1.0,
|
||||
"other_text_size_v": 1.0,
|
||||
"other_text_thickness": 0.15,
|
||||
"other_text_upright": false,
|
||||
"pads": {
|
||||
"drill": 0.8,
|
||||
"height": 1.27,
|
||||
"width": 2.54
|
||||
},
|
||||
"silk_line_width": 0.1,
|
||||
"silk_text_italic": false,
|
||||
"silk_text_size_h": 1.0,
|
||||
"silk_text_size_v": 1.0,
|
||||
"silk_text_thickness": 0.1,
|
||||
"silk_text_upright": false,
|
||||
"zones": {
|
||||
"border_display_style": 2,
|
||||
"border_hatch_pitch": 0.5,
|
||||
"corner_radius": 0.0,
|
||||
"corner_smoothing": 0,
|
||||
"fill_mode": 0,
|
||||
"hatch_gap": 1.5,
|
||||
"hatch_orientation": 0.0,
|
||||
"hatch_smoothing_level": 0,
|
||||
"hatch_smoothing_value": 0.1,
|
||||
"hatch_thickness": 1.0,
|
||||
"min_clearance": 0.5,
|
||||
"min_island_area": 10.0,
|
||||
"min_thickness": 0.25,
|
||||
"pad_connection": 1,
|
||||
"remove_islands": 0,
|
||||
"thermal_relief_gap": 0.5,
|
||||
"thermal_relief_spoke_width": 0.5
|
||||
}
|
||||
},
|
||||
"diff_pair_dimensions": [],
|
||||
"drc_exclusions": [],
|
||||
"meta": {
|
||||
"version": 2
|
||||
},
|
||||
"rule_severities": {
|
||||
"annular_width": "error",
|
||||
"clearance": "error",
|
||||
"connection_width": "warning",
|
||||
"copper_edge_clearance": "error",
|
||||
"copper_sliver": "warning",
|
||||
"courtyards_overlap": "error",
|
||||
"creepage": "error",
|
||||
"diff_pair_gap_out_of_range": "error",
|
||||
"diff_pair_uncoupled_length_too_long": "error",
|
||||
"drill_out_of_range": "error",
|
||||
"duplicate_footprints": "warning",
|
||||
"extra_footprint": "warning",
|
||||
"footprint": "error",
|
||||
"footprint_filters_mismatch": "ignore",
|
||||
"footprint_symbol_field_mismatch": "warning",
|
||||
"footprint_symbol_mismatch": "warning",
|
||||
"footprint_type_mismatch": "ignore",
|
||||
"hole_clearance": "error",
|
||||
"hole_to_hole": "warning",
|
||||
"holes_co_located": "warning",
|
||||
"invalid_outline": "error",
|
||||
"isolated_copper": "warning",
|
||||
"item_on_disabled_layer": "error",
|
||||
"items_not_allowed": "error",
|
||||
"length_out_of_range": "error",
|
||||
"lib_footprint_issues": "warning",
|
||||
"lib_footprint_mismatch": "warning",
|
||||
"malformed_courtyard": "error",
|
||||
"microvia_drill_out_of_range": "error",
|
||||
"mirrored_text_on_front_layer": "warning",
|
||||
"missing_courtyard": "ignore",
|
||||
"missing_footprint": "warning",
|
||||
"missing_tuning_profile": "warning",
|
||||
"net_conflict": "warning",
|
||||
"nonmirrored_text_on_back_layer": "warning",
|
||||
"npth_inside_courtyard": "error",
|
||||
"padstack": "warning",
|
||||
"pth_inside_courtyard": "error",
|
||||
"shorting_items": "error",
|
||||
"silk_edge_clearance": "warning",
|
||||
"silk_over_copper": "warning",
|
||||
"silk_overlap": "warning",
|
||||
"skew_out_of_range": "error",
|
||||
"solder_mask_bridge": "error",
|
||||
"starved_thermal": "error",
|
||||
"text_height": "warning",
|
||||
"text_on_edge_cuts": "error",
|
||||
"text_thickness": "warning",
|
||||
"through_hole_pad_without_hole": "error",
|
||||
"too_many_vias": "error",
|
||||
"track_angle": "error",
|
||||
"track_dangling": "warning",
|
||||
"track_not_centered_on_via": "ignore",
|
||||
"track_on_post_machined_layer": "error",
|
||||
"track_segment_length": "error",
|
||||
"track_width": "error",
|
||||
"tracks_crossing": "error",
|
||||
"tuning_profile_track_geometries": "ignore",
|
||||
"unconnected_items": "error",
|
||||
"unresolved_variable": "error",
|
||||
"via_dangling": "warning",
|
||||
"zones_intersect": "error"
|
||||
},
|
||||
"rules": {
|
||||
"max_error": 0.005,
|
||||
"min_clearance": 0.0,
|
||||
"min_connection": 0.0,
|
||||
"min_copper_edge_clearance": 0.5,
|
||||
"min_groove_width": 0.0,
|
||||
"min_hole_clearance": 0.25,
|
||||
"min_hole_to_hole": 0.25,
|
||||
"min_microvia_diameter": 0.2,
|
||||
"min_microvia_drill": 0.1,
|
||||
"min_resolved_spokes": 2,
|
||||
"min_silk_clearance": 0.0,
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"lib_symbol_issues": "warning",
|
||||
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|
||||
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|
||||
"missing_input_pin": "warning",
|
||||
"missing_power_pin": "error",
|
||||
"missing_unit": "warning",
|
||||
"multiple_net_names": "warning",
|
||||
"net_not_bus_member": "warning",
|
||||
"no_connect_connected": "warning",
|
||||
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|
||||
"pin_not_connected": "error",
|
||||
"pin_not_driven": "error",
|
||||
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|
||||
"power_pin_not_driven": "error",
|
||||
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|
||||
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|
||||
"similar_labels": "warning",
|
||||
"similar_power": "warning",
|
||||
"simulation_model_issue": "ignore",
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"unit_value_mismatch": "error",
|
||||
"unresolved_variable": "error",
|
||||
"wire_dangling": "error"
|
||||
}
|
||||
},
|
||||
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|
||||
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|
||||
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|
||||
},
|
||||
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|
||||
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|
||||
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|
||||
},
|
||||
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|
||||
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|
||||
{
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"name": "Default",
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
}
|
||||
],
|
||||
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|
||||
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|
||||
},
|
||||
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|
||||
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|
||||
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|
||||
},
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"plot": "",
|
||||
"specctra_dsn": "",
|
||||
"vrml": ""
|
||||
},
|
||||
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|
||||
},
|
||||
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|
||||
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|
||||
"annotation": {
|
||||
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|
||||
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|
||||
},
|
||||
"bom_export_filename": "${PROJECTNAME}.csv",
|
||||
"bom_fmt_presets": [],
|
||||
"bom_fmt_settings": {
|
||||
"field_delimiter": ",",
|
||||
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|
||||
"keep_tabs": false,
|
||||
"name": "CSV",
|
||||
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|
||||
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|
||||
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|
||||
},
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
{
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
},
|
||||
{
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
},
|
||||
{
|
||||
"group_by": true,
|
||||
"label": "Value",
|
||||
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|
||||
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|
||||
},
|
||||
{
|
||||
"group_by": true,
|
||||
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|
||||
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|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": true,
|
||||
"label": "Exclude from BOM",
|
||||
"name": "${EXCLUDE_FROM_BOM}",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": true,
|
||||
"label": "Exclude from Board",
|
||||
"name": "${EXCLUDE_FROM_BOARD}",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": true,
|
||||
"label": "Footprint",
|
||||
"name": "Footprint",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": false,
|
||||
"label": "Datasheet",
|
||||
"name": "Datasheet",
|
||||
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|
||||
},
|
||||
{
|
||||
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|
||||
"label": "Check_prices",
|
||||
"name": "Check_prices",
|
||||
"show": false
|
||||
},
|
||||
{
|
||||
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|
||||
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|
||||
"name": "Manufacturer",
|
||||
"show": false
|
||||
},
|
||||
{
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
},
|
||||
{
|
||||
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|
||||
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|
||||
"name": "MP",
|
||||
"show": false
|
||||
},
|
||||
{
|
||||
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|
||||
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|
||||
"name": "Package",
|
||||
"show": false
|
||||
},
|
||||
{
|
||||
"group_by": false,
|
||||
"label": "Price",
|
||||
"name": "Price",
|
||||
"show": false
|
||||
},
|
||||
{
|
||||
"group_by": false,
|
||||
"label": "Purchase-URL",
|
||||
"name": "Purchase-URL",
|
||||
"show": false
|
||||
},
|
||||
{
|
||||
"group_by": false,
|
||||
"label": "SnapEDA_Link",
|
||||
"name": "SnapEDA_Link",
|
||||
"show": false
|
||||
},
|
||||
{
|
||||
"group_by": false,
|
||||
"label": "Availability",
|
||||
"name": "Availability",
|
||||
"show": false
|
||||
},
|
||||
{
|
||||
"group_by": false,
|
||||
"label": "Description",
|
||||
"name": "Description",
|
||||
"show": false
|
||||
},
|
||||
{
|
||||
"group_by": false,
|
||||
"label": "#",
|
||||
"name": "${ITEM_NUMBER}",
|
||||
"show": false
|
||||
}
|
||||
],
|
||||
"filter_string": "",
|
||||
"group_symbols": true,
|
||||
"include_excluded_from_bom": true,
|
||||
"name": "",
|
||||
"sort_asc": true,
|
||||
"sort_field": "Reference"
|
||||
},
|
||||
"bus_aliases": {},
|
||||
"connection_grid_size": 50.0,
|
||||
"drawing": {
|
||||
"dashed_lines_dash_length_ratio": 12.0,
|
||||
"dashed_lines_gap_length_ratio": 3.0,
|
||||
"default_line_thickness": 6.0,
|
||||
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|
||||
"field_names": [],
|
||||
"hop_over_size_choice": 0,
|
||||
"intersheets_ref_own_page": false,
|
||||
"intersheets_ref_prefix": "",
|
||||
"intersheets_ref_short": false,
|
||||
"intersheets_ref_show": false,
|
||||
"intersheets_ref_suffix": "",
|
||||
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|
||||
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|
||||
"operating_point_overlay_i_precision": 3,
|
||||
"operating_point_overlay_i_range": "~A",
|
||||
"operating_point_overlay_v_precision": 3,
|
||||
"operating_point_overlay_v_range": "~V",
|
||||
"overbar_offset_ratio": 1.23,
|
||||
"pin_symbol_size": 25.0,
|
||||
"text_offset_ratio": 0.15
|
||||
},
|
||||
"legacy_lib_dir": "",
|
||||
"legacy_lib_list": [],
|
||||
"meta": {
|
||||
"version": 1
|
||||
},
|
||||
"page_layout_descr_file": "",
|
||||
"plot_directory": "",
|
||||
"reuse_designators": true,
|
||||
"subpart_first_id": 65,
|
||||
"subpart_id_separator": 0,
|
||||
"top_level_sheets": [
|
||||
{
|
||||
"filename": "re-bba-rb.kicad_sch",
|
||||
"name": "ReBBaRb",
|
||||
"uuid": "dbb182a6-d579-468e-b98b-6f0950da9e3a"
|
||||
}
|
||||
],
|
||||
"used_designators": "#PWR0ffa1,J1-4,#PWR04cfa1,#PWR019b1,#PWR05fc1,#PWR0d1,#PWR0c80c1,R1-18,#PWR0670d1,L1,#PWR0d9d1,#PWR0e1,#PWR035b1,#PWR0Y1-2,#PWR0C1,C1-60,#FLG0USBVBUS1,#PWR08d1,#FLG0USBGND1,#PWR1-41,#PWR45,Y1-2,#FLG0GC3V1,#PWR0772b1,#PWR03d6c1,FB1-3,#FLG01V2ETH1,#PWR076f1,#PWR07dc1,#PWR091b1,#FLG012VEXI1,X1,U1-13,#PWR04fe1,#FLG0SP13V1,#PWR03bde1,#PWR06d1,#PWR0eff1,#PWR090e1,#PWR064c1-2,#PWR0AD1-4,#PWR0fa1-2,#FLG0VPHY1,D1,#PWR082e1,#PWR0b0ce1,#PWR0fb6f1,#PWR0df1,#PWR0SW1-2,#PWR050d1,#PWR0f3c1,#PWR0f1,#PWR0b4ee1,#PWR0c3b1,#PWR0cb1,#PWR09e1,#PWR0a5b1",
|
||||
"variants": []
|
||||
},
|
||||
"sheets": [
|
||||
[
|
||||
"dbb182a6-d579-468e-b98b-6f0950da9e3a",
|
||||
"ReBBaRb"
|
||||
],
|
||||
[
|
||||
"69f32f10-d46b-43fd-9030-7f4135d40b78",
|
||||
"Power"
|
||||
],
|
||||
[
|
||||
"64033f5d-a512-44d7-9483-4c31ef84bd56",
|
||||
"Usb Connector"
|
||||
],
|
||||
[
|
||||
"73763384-ff95-4826-8da6-2de53070e62f",
|
||||
"fpga"
|
||||
],
|
||||
[
|
||||
"c2ddb95f-8a63-4bb0-b3f2-a27a372fea3a",
|
||||
"ethernet"
|
||||
],
|
||||
[
|
||||
"1b071f68-b4ea-469c-942f-de06380c9077",
|
||||
"exi"
|
||||
]
|
||||
],
|
||||
"text_variables": {},
|
||||
"tuning_profiles": {
|
||||
"meta": {
|
||||
"version": 0
|
||||
},
|
||||
"tuning_profiles_impedance_geometric": []
|
||||
}
|
||||
}
|
||||
Reference in New Issue
Block a user