Fixes the power traces.

hardware/re-bba-rb/re-bba-rb.kicad_dru

@@ -8,3 +8,19 @@
 (rule "SP1 gold fingers - allow copper to board edge"
 	(condition "A.memberOfFootprint('J3') || B.memberOfFootprint('J3')")
 	(constraint edge_clearance (min -0.5mm)))
+
+# Power-integrity: flag any power-rail track narrower than its netclass width.
+# A netclass "track width" is only the DEFAULT for new routing - KiCad does NOT
+# enforce it - so without these rules an under-width power trace passes DRC
+# silently. These make DRC surface every thin power segment so they don't have to
+# be found by eye. Severity is "warning" (not error) so an unavoidable neck into a
+# fine-pitch pin is flagged for review but never blocks fab export.
+(rule "Power rail minimum width (0.3mm)"
+	(severity warning)
+	(condition "A.NetClass == 'Power'")
+	(constraint track_width (min 0.3mm)))
+
+(rule "Low-current power rail minimum width (0.25mm)"
+	(severity warning)
+	(condition "A.NetClass == 'PowerLV'")
+	(constraint track_width (min 0.25mm)))