Cut the MISO output path: drop EXI_J4 and the CS mux; rank seeds by it
Remaining after the bit-phase fix was a SPEED-DEPENDENT failure -- the GC read
correctly at 1/2/4/8/16 MHz and failed only at index 5 (27 MHz), returning
0B 80 = 0x17 late by exactly ONE bit. Opposite signature to the phase slip it
was hiding under, and this one really is propagation delay.
MISO is source-synchronous: driven on the falling edge, sampled by the GC on
the next rising edge, so the whole path must fit a HALF period -- 18.5 ns at
27 MHz -- minus global-buffer insertion, pad, connector and the GC's setup.
The failing build measured ~10.5 ns of that internally. Critical path:
clk-to-q 1.39 tx_shift (3,12)
routing 3.60 tx_shift[7] (3,12) -> (5,5) to the CS mux
logic 1.21 Mux(cs_n, 1, ...) LUT
routing 4.79 miso (5,5) -> (17,0) to the J4 MISO pad
10.99 ns (2.60 logic, 8.39 routing)
Two removals, both of things that were pure cost here:
1. EXI_J4 is GONE entirely (exi_j4.py, the resource, the AND merge, the docs
section, scripts/pi-exi-wirecheck.py) -- recoverable from git history. The
AND put a LUT in the CLOCK path, denying the EXI clock pad its dedicated
global-buffer route, and MISO fanned out to the J4 pad at die (17,0) which
was the far end of the critical output path: 4.79 ns of routing to a header
with nothing plugged into it. 10.2-11.5 ns -> 9.3-9.6 ns.
2. The Mux(cs_n, 1, ...) LUT is gone from the MISO data path. It only parked
MISO high when deselected, which the flop's own reset value does for free:
tx_shift now has init=0xFF and CS is that domain's async reset, so MISO is
tx_shift[7] with nothing in between. Removes 1.21 ns of logic plus the
3.60 ns route feeding it and lets the placer sit the flop by the pad.
synth.py now PARSES AND RANKS BY the MISO clock-to-pad delay. Ranking by fmax
was how a board that failed at 27 MHz passed every seed at >=1.29x margin --
fmax was never the binding constraint for this design.
--seeds 8: clk 28.7-32.5 MHz, EXI 49.6-62.1 MHz, MISO 8.38-10.22 ns, 8/8 PASS.
Best seed 8 (clk 30.35, EXI 49.56, MISO 8.38 ns), flashed.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
This commit is contained in:
+61
-86
@@ -102,42 +102,11 @@ _UART_TX, _UART_RX = ("9", "10") if os.environ.get("UART_J4") else ("19", "18")
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# full UART_J4 design. Default = 28 (real board). See BRINGUP.md.
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_ETH_D3 = os.environ.get("ETH_D3_PIN", "28")
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# EXI bring-up on the J4 debug header (set env EXI_J4=1). Rather than REPINNING
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# the EXI resource onto J4 -- which moves where the capture domain anchors on the
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# die -- this MERGES a second set of EXI pads onto the existing ones, so the SP1
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# edge connector stays live and the normal build is one env var away.
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#
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# J4.1 = GND
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# J4.2 = DBG0 = FPGA pin 9 -> EXI CLK (in)
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# J4.3 = DBG1 = FPGA pin 10 -> EXI MOSI (in)
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# J4.4 = DBG2 = FPGA pin 11 -> EXI MISO (out)
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# J4.5 = DBG3 = FPGA pin 12 -> EXI CS_N (in)
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# J4.6 = DBG4 = FPGA pin 6 -> EXI INT_N (out)
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#
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# The three INPUTS are merged with AND. That is correct precisely because every
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# EXI input is idle/inactive HIGH: CPOL=1 so CLK idles high, CS_N is active-low,
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# and MOSI only matters while CS_N is low. Whichever side is unplugged sits at 1
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# through its SB_IO PULLUP and passes the other side through untouched, so no
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# select signal is needed. Both pad sets therefore get PULLUP=1 in this build.
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# DRIVE ONE SIDE AT A TIME -- a GameCube on SP1 and a host on J4 at the same time
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# will fight, and the AND will hand the capture engine the mangled product.
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# The two OUTPUTS are simply driven onto both pads (fanout 2, no added logic).
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#
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# Timing: all five J4 pads are on the SAME (bottom) die edge as the EXI pads
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# (x=13..18 vs x=5..9, both y=0), so the capture domain keeps its bottom-edge
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# anchor -- this does not recreate the cross-die span described in CLAUDE.md.
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# It still adds 3 LUTs ahead of the input synchronisers and a second MISO load,
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# and capture has little margin, so ALWAYS sweep seeds on an EXI_J4 build.
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# COLLIDES WITH: UART_J4 (pins 9/10) and ETH_D3_PIN if pointed at a J4 pad.
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_EXI_J4 = bool(os.environ.get("EXI_J4"))
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if _EXI_J4 and os.environ.get("UART_J4"):
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raise SystemExit("EXI_J4 and UART_J4 both claim J4 pins 9/10 - pick one")
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if _EXI_J4 and _ETH_D3 in ("9", "10", "11", "12", "6"):
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raise SystemExit(f"EXI_J4 conflicts with ETH_D3_PIN={_ETH_D3} on the J4 header")
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# EXI pad attributes. No PULLUP: the GameCube drives all three inputs
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# through the SP1 edge connector.
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_EXI_ATTRS = Attrs(IO_STANDARD="SB_LVCMOS")
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# With the merge active the unplugged side must idle high rather than float.
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_EXI_ATTRS = (Attrs(IO_STANDARD="SB_LVCMOS", PULLUP=1) if _EXI_J4
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else Attrs(IO_STANDARD="SB_LVCMOS"))
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class IceBreakerPlatform(LatticeICE40Platform):
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@@ -160,15 +129,6 @@ class IceBreakerPlatform(LatticeICE40Platform):
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Subsignal("int_n", Pins("46", dir="o")),
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_EXI_ATTRS),
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# EXI mirror on the J4 debug header (EXI_J4=1 only) -- see note above.
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*([Resource("exi_j4", 0,
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Subsignal("clk", Pins("9", dir="i")),
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Subsignal("mosi", Pins("10", dir="i")),
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Subsignal("miso", Pins("11", dir="o")),
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Subsignal("cs_n", Pins("12", dir="i")),
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Subsignal("int_n", Pins("6", dir="o")),
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_EXI_ATTRS)] if _EXI_J4 else []),
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# W5100 indirect parallel bus
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Resource("w5100", 0,
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Subsignal("addr", Pins("42 38", dir="o")),
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@@ -233,46 +193,23 @@ class BBATopSynth(BBATop):
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exi = platform.request("exi", 0)
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w5100 = platform.request("w5100", 0)
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# EXI inputs: optionally AND-merged with the J4 header mirror so a
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# bench host can drive EXI without the SP1 edge connector. AND is
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# valid because all three inputs are inactive-HIGH and the unused
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# side is held there by its SB_IO PULLUP -- see the _EXI_J4 note.
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if _EXI_J4:
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j4 = platform.request("exi_j4", 0)
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exi_clk_i = exi.clk.i & j4.clk.i
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exi_mosi_i = exi.mosi.i & j4.mosi.i
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exi_cs_n_i = exi.cs_n.i & j4.cs_n.i
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m.d.comb += [
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j4.miso.o .eq(self.exi_miso),
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j4.int_n.o .eq(self.int_n),
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]
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else:
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exi_clk_i, exi_mosi_i, exi_cs_n_i = exi.clk.i, exi.mosi.i, exi.cs_n.i
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# The EXI clock pin now clocks the bit engine directly (see
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# BBATop's clock-domain comment), so it is a REAL clock net and
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# must be constrained. Without this nextpnr defaults it to
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# 12 MHz and happily reports PASS on a build that would miss bits
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# on a console. The GC tops out at ~27 MHz ("EXI_SPEED32MHZ" is a
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# nominal name, not the actual rate).
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# Constrain the net that actually BECOMES the clock, which
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# differs between the two build variants:
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# plain -- self.exi_clk is a pure alias of the pad and yosys
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# absorbs it, leaving the pad net (nextpnr calls it
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# 'exi_0__clk__i_$glb_clk').
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# EXI_J4 -- the clock is the AND of the two pads, a distinct net
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# ('exi_clk_$glb_clk'); constraining either pad then
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# misses, and nextpnr silently falls back to its 12 MHz
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# default and under-optimises the whole EXI domain.
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if _EXI_J4:
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platform.add_clock_constraint(self.exi_clk, _EXI_HZ)
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else:
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platform.add_clock_constraint(exi.clk.i, _EXI_HZ)
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# Constrain the pad that becomes the clock. self.exi_clk is a
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# pure alias of it and yosys absorbs the alias, so the surviving
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# net is the pad's ('exi_0__clk__i_$glb_clk'). Without this
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# nextpnr defaults the clock to 12 MHz and reports PASS on a build
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# that would miss bits on a console.
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platform.add_clock_constraint(exi.clk.i, _EXI_HZ)
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m.d.comb += [
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self.exi_clk .eq(exi_clk_i),
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self.exi_mosi .eq(exi_mosi_i),
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self.exi_cs_n .eq(exi_cs_n_i),
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self.exi_clk .eq(exi.clk.i),
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self.exi_mosi .eq(exi.mosi.i),
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self.exi_cs_n .eq(exi.cs_n.i),
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exi.miso.o .eq(self.exi_miso),
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exi.int_n.o .eq(self.int_n),
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@@ -419,6 +356,7 @@ if __name__ == "__main__":
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best_seed = 1
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best_fmax = 0.0
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best_detail = None
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best_miso = None
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results = [] # (seed, fmax_clk, fmax_exi, verdict), scored only
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for seed in range(1, n_seeds + 1):
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print(f"\n{'='*60}")
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@@ -472,6 +410,7 @@ if __name__ == "__main__":
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# 49.66 MHz: unparsed seeds silently mixed with real ones. An
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# unparseable seed must be reported and skipped, never ranked.
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fmax = {}
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out_ns = [None] # MISO clock-to-pad, post-route
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for tf in sorted(set(glob.glob(f"{build_dir}/*.tim"))):
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try:
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# errors="replace": a decode hiccup must not abort the parse
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@@ -482,6 +421,21 @@ if __name__ == "__main__":
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r"Max frequency for clock\s+'([^']+)':\s*([\d.]+)\s*MHz", line)
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if m_:
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fmax[m_.group(1)] = float(m_.group(2))
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# MISO clock-to-pad. fmax is NOT the binding
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# constraint for this design: every seed passed both
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# fmax targets with >=1.29x margin while the BOARD
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# still failed at 27 MHz, because MISO is a
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# source-synchronous output -- it leaves on the
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# falling edge and the GameCube samples it on the
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# next rising edge, so the whole path must fit a
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# HALF period (18.5 ns at 27 MHz) minus global-buffer
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# insertion, pad, connector and the GC's own setup.
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# Track it explicitly and rank on it.
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m_ = re.search(
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r"Max delay\s+negedge\s+\S+\s*->\s*<async>\s*:"
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r"\s*([\d.]+)\s*ns", line)
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if m_:
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out_ns[0] = float(m_.group(1))
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except OSError as exc:
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print(f" [seed {seed}] could not read {tf}: {exc}")
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@@ -500,7 +454,7 @@ if __name__ == "__main__":
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fmax_clk, fmax_exi = fmax["clk"], fmax[exi_keys[0]]
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verdict = ("PASS" if fmax_exi >= _EXI_TARGET and fmax_clk >= 24.0
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else "FAIL")
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results.append((seed, fmax_clk, fmax_exi, verdict))
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results.append((seed, fmax_clk, fmax_exi, verdict, None))
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print(f" [seed {seed}] clk fmax: {fmax_clk:.2f} MHz (target 24) "
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f"exi fmax: {fmax_exi:.2f} MHz (target {_EXI_TARGET}) "
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f"{verdict}"
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@@ -510,30 +464,51 @@ if __name__ == "__main__":
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# with the PLL gone the EXI domain has ~2.3x margin and `clk` can
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# easily be the tighter of the two, so ranking by EXI alone would pick
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# a seed that is worse overall.
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# Rank by the SMALLEST MISO clock-to-pad delay among seeds that meet
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# both fmax targets -- that is the constraint that actually failed on
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# hardware. Fall back to relative fmax margin only if the delay could
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# not be parsed.
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miso = out_ns[0]
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if verdict == "PASS" and miso is not None:
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if best_miso is None or miso < best_miso:
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best_miso = miso
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best_seed = seed
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best_detail = (fmax_clk, fmax_exi, miso)
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score = min(fmax_exi / _EXI_TARGET, fmax_clk / 24.0)
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if score > best_fmax:
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best_fmax = score
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best_seed = seed
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best_detail = (fmax_clk, fmax_exi)
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if best_miso is None:
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best_seed = seed
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best_detail = (fmax_clk, fmax_exi, miso)
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results[-1] = (seed, fmax_clk, fmax_exi, verdict, miso)
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# Per-seed summary. The pass RATE matters as much as the best number — a
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# design that only closes on a minority of seeds has no real margin.
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print(f"\n{'='*60}")
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print(f" Seed sweep summary ({len(results)}/{n_seeds} seeds scored)")
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print(f"{'='*60}")
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print(f" {'seed':>4} {'clk (≥24)':>10} {f'exi (≥{_EXI_TARGET})':>16} verdict")
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for seed, fc, fexi, verdict in results:
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print(f" {seed:>4} {fc:>10.2f} {fexi:>16.2f} {verdict}")
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n_pass = sum(1 for *_, v in results if v == "PASS")
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print(f" {'seed':>4} {'clk (≥24)':>10} {f'exi (≥{_EXI_TARGET})':>16}"
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f" {'MISO clk→pad':>13} verdict")
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for seed, fc, fexi, verdict, miso in results:
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ms = f"{miso:.2f} ns" if miso is not None else " n/a"
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print(f" {seed:>4} {fc:>10.2f} {fexi:>16.2f} {ms:>13} {verdict}")
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n_pass = sum(1 for r in results if r[3] == "PASS")
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if results:
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print(f"\n passing seeds: {n_pass}/{len(results)} "
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f"({[s for s, *_, v in results if v == 'PASS']})")
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f"({[r[0] for r in results if r[3] == 'PASS']})")
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overall = "PASS" if best_fmax >= 1.0 else "FAIL"
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if best_detail:
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ms = (f", MISO clk→pad {best_detail[2]:.2f} ns"
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if best_detail[2] is not None else "")
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print(f"\nBest seed: {best_seed} clk {best_detail[0]:.2f} MHz, "
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f"exi {best_detail[1]:.2f} MHz "
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f"(worst margin {best_fmax:.2f}x) — {overall}")
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f"exi {best_detail[1]:.2f} MHz{ms} — {overall}")
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if best_detail[2] is not None and best_detail[2] > 12.0:
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print(" ⚠️ MISO clk→pad > 12 ns. At 27 MHz the GameCube samples "
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"MISO a HALF period (18.5 ns) after the falling edge it is "
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"driven on, and global-buffer insertion, the pad, the "
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"connector and the GC's setup all come out of what is left. "
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"Reads failed at index 5 and passed at 16 MHz with 10.99 ns.")
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else:
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print(f"\nBest seed: {best_seed} — {overall}")
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if overall == "PASS" and n_pass * 2 < len(results):
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