Fixes review comments.

hardware/re-bba-rb/TODO.md

@@ -206,6 +206,30 @@ Major work this session:
       at (148.49, 61.7225) near U11 pin 48. Verified 2026-07-22: nets
       `/ethernet/ETH_RST` + `/ethernet/ETH_3V3` both present on the footprint,
       0 unconnected items.
+- [ ] **12 V inrush limiter (U13 TPS25961 eFuse) — SCHEMATIC DONE 2026-07-31**,
+      full design rationale in REVIEW.md §6. J3.5 → 12V_RAW → U13 → 12V_EXI;
+      D3 (TVS) stays upstream, C65 downstream. R45 100 k sets I_LIM ≈ 500 mA
+      (caps inrush, 3.8× the ~130 mA steady-state load); R46/R47 620 k/100 k
+      set UVLO ≈ 8.9 V; C66 100 nF is Cin. U13 = TPS25961DRVR, **LCSC
+      C5571272**.
+      - [ ] **PCB: place + route U13, R45, R46, R47, C66.** Two datasheet
+            requirements to honour in layout: (1) the **thermal pad must
+            connect to the GND plane** — the footprint is the `_ThermalVias`
+            variant, confirm the vias actually reach In1/In2 GND; (2) **OVLO
+            absolute max is 6.5 V** and it is tied to GND for the internal
+            fixed threshold — that connection must be solid and must never
+            see 12 V. Keep C66 close to U13's IN pin.
+      - [ ] **Select parts for R45 (100 k), R46 (620 k), R47 (100 k), C66
+            (100 nF)** — fields intentionally left blank. R45/R47 can reuse
+            the UNI-ROYAL 100 k C25741 already used by R4 (NOT C60490 - that part
+            is 10 k, an earlier note in this file had it wrong).
+            **Do not round R45 into 58.8–66.7 kΩ, 111–142 kΩ or 250–500 kΩ**
+            (datasheet Table 7-1 forbidden ON-resistance bins).
+      - [ ] **Bench: verify inrush at GC power-on** — expect ≈500 mA for
+            ~2.9 ms (was ~621 mA slew-limited, unbounded before the eFuse).
+            Also confirm no retry/motorboating at startup; if the rail sags
+            more than expected, that points at SP1 connector/cable impedance,
+            not the UVLO setting.
 - [ ] **Gateware: gate all outputs on GC_ON** — when GC_ON=0 the W5100S is
       unpowered (U12) and the GC is off, but FPGA banks stay at 3.3 V. Hold
       the W5100S bus and EXI outputs Hi-Z/low to avoid back-powering.
@@ -327,10 +351,21 @@ Major work this session:
       WIZnet's own reference synthesizes it as 12 k + 300 Ω. The 0.8 %
       deviation on a bandgap bias resistor is immaterial (well under the
       combined tolerance of the ref design's two 1 % parts).
-- [x] Crystals Y1/Y2 — VERIFIED 2026-07-17: the BOM parts are both CL = 12 pF
-      (Y1 YXC X322512MOB4SI / C70565, Y2 X322525MOB4SI / C9006, both JLC
-      Basic, ±10 ppm) — correct for the 18 pF load caps and the W5100S
-      Table 9 recommendation. No change needed.
+- [x] Crystals Y1/Y2 — VERIFIED 2026-07-17, **RE-CONFIRMED 2026-07-31**: the
+      BOM parts are both CL = 12 pF (Y1 YXC X322512MOB4SI / C70565,
+      Y2 X322525MOB4SI / C9006, both JLC Basic, ±10 ppm) — correct for the
+      18 pF load caps (`CL = C/2 + Cstray` → 18/2 + 3 = 12 pF exactly).
+      **This entry was right; a 2026-07-31 attempt to change the caps to
+      30 pF/10 pF was a regression and has been reverted.** The cause was
+      wrong `CL` metadata in the schematic symbol properties (Y1 said 18 pF,
+      Y2 said 8 pF) — properties are now corrected to the real specs from
+      `datasheets/Ysx321SL.pdf`. Do not change the crystal caps.
+      Note: the "W5100S Table 9 recommendation" citation above is fragile —
+      Table 9 says 12 pF but **Table 8 says 8 pF**, and the DS revision
+      history logs "Modified Load capacitance value (12p → 8p)". The fitted
+      12 pF part therefore matches the *stale* table. Accepted as a
+      documented deviation (frequency accuracy unaffected; gain margin 7.75×
+      with R44) — see REVIEW.md §5.
 - [x] 12 V-rail parts ≥ 25 V — VERIFIED in BOM audit 2026-07-17: C3/C4 25 V,
       C6 50 V, C65 25 V (Lelon SMD electrolytic); D3 SMAJ12A correct.
 - [x] 1 % tolerance — VERIFIED in BOM audit 2026-07-17: R1/R2, R3/R4, R10,
@@ -346,6 +381,19 @@ Major work this session:
       separates chassis via 1 nF/2 kV — acceptable choice, confirm intent).
 - [ ] Confirm at bring-up (from CLAUDE.md): W5100S register addresses / MR
       bits were written from memory.
+- [ ] **Measure Y2 crystal drive level at bring-up and tune R44 (RExt).**
+      Added 2026-07-31 at **49.9 Ω** (gain margin 7.53×, DS requires ≥5;
+      **ceiling 100 Ω**, 120 Ω fails startup). Reason it exists: the fitted
+      crystal is rated **DL = 200 µW max** but W5100S Table 9 says select a
+      **500 µW** part, so the chip can overdrive it ~2.5×. Part fields are
+      deliberately blank — confirm the value on the bench (scope the crystal,
+      compute DL) before committing a BOM line. If drive is comfortably under
+      200 µW a smaller value (or 0 Ω, per the WIZnet reference) is fine; if
+      it's high, go up but stay ≤100 Ω. See REVIEW.md §5.
+- [ ] **Select a part for R43** (EE_CS 10 kΩ pull-down, added 2026-07-31).
+      Any 10 kΩ 0402 works — the in-stock YAGEO RC0402FR-0710KL / C60490
+      already used on R2/R5/R18/R31/R36 is the obvious choice; fields were
+      left blank so it doesn't silently inherit an out-of-stock part.
 
 ## JLCPCB ordering notes (DRC clean — these are order-form options)