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Fixes review comments.

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This commit is contained in:
Dennis Brentjes
2026-07-31 11:46:07 +02:00
parent 5828d6a388
commit 7d7ab34bff
23 changed files with 15412 additions and 7499 deletions
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.gitignore
+1
View File
@@ -19,6 +19,7 @@ fp-info-cache
_autosave-*
.history/
hardware/re-bba-rb/gerbers
hardware/sp1_insert/gerbers
*-bom.csv
*-cpl.csv
CLAUDE.md
+34 -8
View File
@@ -75,9 +75,28 @@ icepll -i 12 -o 54 # confirms DIVR=0 DIVF=71 DIVQ=4 → 54 MHz (capture domai
The `exi_bba/` module tree is **fully implemented** with simulation testbenches.
All modules elaborate without errors and pass their unit tests. The full design
**synthesizes, places, routes, and meets timing** on the iCE40UP5K
(`python -m exi_bba.synth`): `capture` closes ~70 MHz (target 54) and `exi`/
`sync` close ~36 MHz (target 24) — both PASS.
synthesizes, places and routes on the iCE40UP5K, but **capture-domain timing is
seed-dependent and only closes on a minority of seeds** — you MUST sweep.
Measured 2026-07-31, full build (`BBATopSynth(status_panel=True,
uart_console=True)`, 47% LC), `python -m exi_bba.synth --seeds 8`:
| domain | target | result |
|---|---|---|
| `clk` (exi/sync) | 24 MHz | 35.4–38.4 MHz — **PASS on every seed** |
| `capture_clk` | 54.02 MHz | 49.7–55.7 MHz — **PASS on only 2 of 8 seeds** (3 and 6) |
Best seed 3 = 55.69 MHz, margin +1.67 MHz (3%). Seed 1 — the default when you
run without `--seeds` — **FAILS at 53.08 MHz**. So `python -m exi_bba.synth`
with no arguments produces a bitstream that does not meet timing; always pass
`--seeds 8` (or more) and flash the reported best seed from
`build/seed<N>/top.bin`.
There is essentially no margin: assume any added logic breaks capture timing
until a sweep proves otherwise. The earlier "~70 MHz, both PASS" figure in this
file was wrong — it came from a sweep that silently never ran (see the
`_prepared` note in `synth.py`) and from misreading nextpnr's PRE-routing
placement estimate, which runs ~8 MHz optimistic.
### `exi_bba/` module status
@@ -98,10 +117,15 @@ All modules elaborate without errors and pass their unit tests. The full design
**Bring-up status panel (optional):** `BBATop(status_panel=True)` adds a
`StatusPanel` driving onboard iCEbreaker LEDs + button (dedicated pins, so it
coexists with EXI + W5100). `synth.py` enables it: **LEDG=heartbeat**,
**LEDR=EXI activity** (the GC is talking), **RGB red=rx / green=tx / blue=ready**
**LEDR=EXI activity** (the GC is talking), **RGB red=rx / green=tx / ready**
(via `SB_RGBA_DRV` on pins 39/40/41), **BTN_N=manual re-init**. All 5 panel
LEDs are now mapped on the iCEbreaker. The full EXI + W5100 + panel build
synthesizes and meets timing (slow ~35≥24, capture ~64≥54, 44% LC).
LEDs are now mapped on the iCEbreaker. For this build's timing see the seed
table above — it does NOT close on every seed.
On the **re-bba-rb board** the third RGB element (`led[4]`, "ready", pin 41) is
**D13 = YELLOW** (LCSC C2287), not blue — `synth.py`'s comment still calls it
blue, which describes the iCEbreaker dev board, not this PCB. D11=RED (rx) and
D12=GREEN (tx) are correct on both.
**Ethernet back-end is selectable:** `BBATop(eth="w5100")` (default — indirect
parallel bus, reaches the ~27 Mbit/s EXI ceiling) or `BBATop(eth="w5500")` (SPI,
@@ -124,8 +148,10 @@ python -m exi_bba.bba_top # end-to-end EXI integration test (W5100 RX loo
```
### Pending work
- **Synthesis/timing**: ✅ done — `python -m exi_bba.synth` synthesizes, P&Rs,
and meets timing on both clock domains (capture ~68≥54, slow ~40≥24).
- **Synthesis/timing**: ⚠️ partially — synthesizes and P&Rs, `clk` closes with
wide margin, but `capture_clk` closes on only **2 of 8 seeds** and the default
seed 1 FAILS (53.08 < 54.02). Always `--seeds 8`. Reducing capture-domain
logic to get a real margin is still open work — see the seed table above.
- **W5500 init/TX/RX**: ✅ done — `W5500SPIMaster` has a real Mode-0 byte engine,
a generic register-transaction engine (header + wbuf/stream payload), the full
init sequence (MR reset, SHAR, S0_MR MACRAW, S0_CR OPEN, S0_IMR), MACRAW TX
exi_bba/synth.py
+103 -25
View File
@@ -8,7 +8,9 @@ This file re-declares IceBreakerPlatform inline so that importing
rebbarb/rebbarb.py (which has a module-level platform.build() call) is avoided.
"""
import glob
import os
import re
import subprocess
import sys
@@ -42,8 +44,10 @@ from exi_bba.bba_top import BBATop
# total (per icestorm's icebox.py pin database), and every other one is
# already assigned to a real signal on this board — pin 13 shows up in the
# schematic netlist as an unrouted U9 pad, nothing else was available.
# Board is still in design, so PIN 13 ON THE SCHEMATIC/PCB MUST BE REWORKED
# to carry ETH_INT instead of pin 35 before layout is final.
# DONE on the board: the schematic + PCB now carry /ethernet/ETH_INT on U9
# pin 13, and pin 35 is left unconnected (net
# "unconnected-(U9A-IOT_46b_G0-Pad35)") so the PLL hard macro can claim it.
# Verified against the schematic netlist 2026-07-31 — do not "restore" pin 35.
#
# Debug (J4 header, unpopulated): DBG0=9 DBG1=10 DBG2=11 DBG3=12 DBG4=6
# UART (FT2232H channel B): net UART_TXD is the FTDI's OUTPUT, so it is the
@@ -205,63 +209,137 @@ if __name__ == "__main__":
n_seeds = next((int(sys.argv[i+1]) for i, a in enumerate(sys.argv)
if a == "--seeds"), 1)
platform = IceBreakerPlatform()
print(f"Synthesizing BBATop for {platform.device}-{platform.package} "
print(f"Synthesizing BBATop for {IceBreakerPlatform.device}-"
f"{IceBreakerPlatform.package} "
f"(do_program={do_flash}, seeds=1..{n_seeds})")
best_seed = 1
best_fmax = 0.0
results = [] # (seed, fmax_clk, fmax_capture, verdict), scored only
for seed in range(1, n_seeds + 1):
print(f"\n{'='*60}")
print(f" Seed {seed}/{n_seeds}")
print(f"{'='*60}")
opts = (f"--opt-timing --seed {seed} --timing-allow-fail")
# A Platform instance can only be built ONCE — amaranth's
# TemplatedPlatform.prepare() does `assert not self._prepared`. Reusing
# one platform across the sweep made seeds 2..N raise a bare
# AssertionError (empty message, so the handler below printed nothing),
# after which the fmax parser re-read the PREVIOUS seed's build/top.tim
# and reported identical numbers for every seed — a sweep that looked
# like it ran but never did. Build a fresh platform per seed.
platform = IceBreakerPlatform()
# Each seed gets its OWN build directory. Sharing one `build/top.tim`
# across the sweep is not safe on this workspace: /workspace is a WSL2
# drvfs (Windows drive) mount, and a re-read of a file just rewritten
# by a child process can return stale or partially-flushed content.
# That silently mis-scored the sweep — seeds were credited with other
# seeds' numbers, including nextpnr's PRE-routing placement estimates
# (which run ~8 MHz optimistic), so a 53.08 MHz FAIL got reported as a
# 61.94 MHz PASS. Deleting the stale file first did NOT fix it; only
# not sharing the path does. Do not "simplify" this back to build/.
build_dir = f"build/seed{seed}"
build_ok = True
try:
platform.build(BBATopSynth(status_panel=True, uart_console=True), do_program=False,
verbose=True, nextpnr_opts=opts)
verbose=True, nextpnr_opts=opts, build_dir=build_dir)
except Exception as exc:
# nextpnr exits non-zero even with --timing-allow-fail on some
# versions; treat as non-fatal timing failure.
print(f" [seed {seed}] build exception (timing?): {exc}")
build_ok = False
print(f" [seed {seed}] build exception (timing?): "
f"{type(exc).__name__}: {exc}")
# Parse fmax from nextpnr log in build/top.tim (if present). Domain
# names are 'clk' (exi/sync, 24 MHz target) and 'capture_clk'
# (54 MHz target, the tighter constraint) — NOT 'exi', which never
# matched any real log line (this regex silently reported 0.0 MHz
# for every seed until fixed).
import glob, re
tim_files = glob.glob("build/top.tim") + glob.glob("build/*.tim")
fmax_clk = 0.0
fmax_capture = 0.0
for tf in tim_files:
# nextpnr reports each domain TWICE: once post-placement (an estimate)
# and once post-routing. Only the post-route number is real, so take
# the LAST occurrence of each domain — never the first.
#
# A seed is only scored if BOTH domains were actually found. Defaulting
# a missing value to 0.0 and scoring it anyway is how this script once
# declared "Best seed: 8 ... PASS" while seed 8 in fact failed at
# 49.66 MHz: unparsed seeds silently mixed with real ones. An
# unparseable seed must be reported and skipped, never ranked.
fmax = {}
for tf in sorted(set(glob.glob(f"{build_dir}/*.tim"))):
try:
with open(tf) as f:
# errors="replace": a decode hiccup must not abort the parse
# and leave the seed looking like a legitimate 0.0 MHz result.
with open(tf, errors="replace") as f:
for line in f:
m_ = re.search(
r"Max frequency for clock\s+'(\w+)':\s*([\d.]+)\s*MHz", line)
if m_:
domain, freq = m_.group(1), float(m_.group(2))
if domain == "clk":
fmax_clk = freq
elif domain == "capture_clk":
fmax_capture = freq
except OSError:
pass
fmax[m_.group(1)] = float(m_.group(2))
except OSError as exc:
print(f" [seed {seed}] could not read {tf}: {exc}")
if "clk" not in fmax or "capture_clk" not in fmax:
print(f" [seed {seed}] NO USABLE TIMING REPORT "
f"(found {sorted(fmax) or 'nothing'}) — NOT SCORED"
f"{'' if build_ok else '; build also reported an error'}")
continue
fmax_clk, fmax_capture = fmax["clk"], fmax["capture_clk"]
verdict = ("PASS" if fmax_capture >= 54.02 and fmax_clk >= 24.0
else "FAIL")
results.append((seed, fmax_clk, fmax_capture, verdict))
print(f" [seed {seed}] clk fmax: {fmax_clk:.2f} MHz (target 24) "
f"capture_clk fmax: {fmax_capture:.2f} MHz (target 54.02)")
f"capture_clk fmax: {fmax_capture:.2f} MHz (target 54.02) "
f"{verdict}"
f"{'' if build_ok else ' [build reported an error]'}")
# capture_clk is the binding constraint (tighter target, historically
# the one that swings ±20% with seed) — rank seeds by it.
if fmax_capture > best_fmax:
best_fmax = fmax_capture
best_seed = seed
print(f"\nBest seed: {best_seed} capture_clk fmax: {best_fmax:.2f} MHz "
f"(target 54.02) — {'PASS' if best_fmax >= 54.02 else 'FAIL'}")
# Per-seed summary. capture_clk swings hard with seed on this design, so
# the pass RATE matters as much as the best number — a design that only
# closes on a minority of seeds has no real margin.
print(f"\n{'='*60}")
print(f" Seed sweep summary ({len(results)}/{n_seeds} seeds scored)")
print(f"{'='*60}")
print(f" {'seed':>4} {'clk (≥24)':>10} {'capture_clk (≥54.02)':>21} verdict")
for seed, fc, fcap, verdict in results:
print(f" {seed:>4} {fc:>10.2f} {fcap:>21.2f} {verdict}")
n_pass = sum(1 for *_, v in results if v == "PASS")
if results:
print(f"\n passing seeds: {n_pass}/{len(results)} "
f"({[s for s, *_, v in results if v == 'PASS']})")
if do_flash:
overall = "PASS" if best_fmax >= 54.02 else "FAIL"
print(f"\nBest seed: {best_seed} capture_clk fmax: {best_fmax:.2f} MHz "
f"(target 54.02) — {overall}")
if overall == "PASS" and n_pass * 2 < len(results):
print(" NOTE: a MINORITY of seeds close timing. The bitstream from "
"the best seed is usable, but this design has little margin — "
"treat any logic addition as likely to break timing.")
# build/ now holds one subdirectory per seed; the flashable bitstream for
# the best seed is build/seed<N>/top.bin. There is no top-level build/top.bin.
if results:
print(f"\nBitstream for best seed: build/seed{best_seed}/top.bin")
if do_flash and overall == "FAIL":
print("\nREFUSING TO FLASH: no seed met the capture-domain timing "
"constraint. The EXI front-end samples a 27 MHz clock and will "
"miss bits. Re-run with more seeds (--seeds 16) or reduce logic.")
elif do_flash:
print(f"\nFlashing with seed {best_seed}...")
opts = f"--opt-timing --seed {best_seed} --timing-allow-fail"
platform.build(BBATopSynth(status_panel=True, uart_console=True), do_program=True,
verbose=True, nextpnr_opts=opts)
# Fresh platform again — the sweep above already consumed one per seed.
# Reuse the best seed's own build dir so the flashed bitstream is the
# one that was actually measured.
IceBreakerPlatform().build(
BBATopSynth(status_panel=True, uart_console=True), do_program=True,
verbose=True, nextpnr_opts=opts, build_dir=f"build/seed{best_seed}")
print("Done.")
hardware/TPS25961.kicad_sym
+191
View File
@@ -0,0 +1,191 @@
(kicad_symbol_lib (version 20211014) (generator kicad_symbol_editor)
(symbol "TPS25961"
(pin_names
(offset 1.016)
)
(exclude_from_sim no)
(in_bom yes)
(on_board yes)
(in_pos_files yes)
(duplicate_pin_numbers_are_jumpers no)
(property "Reference" "U"
(at -10.16 11.43 0)
(show_name no)
(do_not_autoplace no)
(effects
(font
(size 1.27 1.27)
)
(justify left bottom)
)
)
(property "Value" "TPS25961"
(at -10.16 -13.97 0)
(show_name no)
(do_not_autoplace no)
(effects
(font
(size 1.27 1.27)
)
(justify left bottom)
)
)
(property "Footprint" "Package_SON:WSON-6-1EP_2x2mm_P0.65mm_EP1x1.6mm_ThermalVias"
(at 0 0 0)
(hide yes)
(show_name no)
(do_not_autoplace no)
(effects
(font
(size 1.27 1.27)
)
)
)
(property "Datasheet" "https://www.ti.com/lit/ds/symlink/tps25961.pdf"
(at 0 0 0)
(hide yes)
(show_name no)
(do_not_autoplace no)
(effects
(font
(size 1.27 1.27)
)
)
)
(property "Description" "2.7V-19V 106mOhm eFuse, adjustable current limit 0.1-2A, internal 5.17V/ms output slew-rate control, short-circuit and overvoltage protection, 6-pin SON 2x2mm"
(at 0 0 0)
(hide yes)
(show_name no)
(do_not_autoplace no)
(effects
(font
(size 1.27 1.27)
)
)
)
(symbol "TPS25961_0_1"
(rectangle
(start -10.16 10.16)
(end 10.16 -12.7)
(stroke
(width 0.254)
(type default)
)
(fill
(type background)
)
)
)
(symbol "TPS25961_1_1"
(pin power_in line
(at -15.24 7.62 0)
(length 5.08)
(name "IN"
(effects
(font
(size 1.27 1.27)
)
)
)
(number "6"
(effects
(font
(size 1.27 1.27)
)
)
)
)
(pin power_out line
(at 15.24 7.62 180)
(length 5.08)
(name "OUT"
(effects
(font
(size 1.27 1.27)
)
)
)
(number "1"
(effects
(font
(size 1.27 1.27)
)
)
)
)
(pin input line
(at -15.24 0 0)
(length 5.08)
(name "EN/UVLO"
(effects
(font
(size 1.27 1.27)
)
)
)
(number "5"
(effects
(font
(size 1.27 1.27)
)
)
)
)
(pin input line
(at -15.24 -5.08 0)
(length 5.08)
(name "OVLO"
(effects
(font
(size 1.27 1.27)
)
)
)
(number "2"
(effects
(font
(size 1.27 1.27)
)
)
)
)
(pin passive line
(at 15.24 -5.08 180)
(length 5.08)
(name "ILIM"
(effects
(font
(size 1.27 1.27)
)
)
)
(number "3"
(effects
(font
(size 1.27 1.27)
)
)
)
)
(pin power_in line
(at 0 -17.78 90)
(length 5.08)
(name "GND"
(effects
(font
(size 1.27 1.27)
)
)
)
(number "4"
(effects
(font
(size 1.27 1.27)
)
)
)
)
)
(embedded_fonts no)
)
)
hardware/re-bba-rb/CPL_ROTATIONS.md
+98 -14
View File
@@ -32,11 +32,31 @@ the user reports "needs N degrees clockwise", the correction applied is
**`new = (old - N) % 360`**, not `+N`. Get this backwards and every fix
lands 2×N off instead of correct.
## How the correction was (re-)applied each time
## How to reapply — copy this exact dict, don't reconstruct it from memory
This is the complete, current correction set (all 16 parts). **Copy-paste
this block, don't retype it from the table below or from memory** — the one
time it was retyped from a section of prose instead of copied whole, U4 got
silently dropped and shipped with a wrong rotation.
```python
import csv
corrections = { 'REF': degrees, ... } # positive = CCW, negative = CW
corrections = {
'U7': 270, # SOIC-8, confirmed 2026-07-31 (net of +90 hypothesis + 180 more) — same net correction as U10
'U10': 270, # SOIC-8, confirmed (net of +90 hypothesis + 180 more)
'U11': -90, # LQFP-64, confirmed 2026-07-31 ("90 degrees clockwise") — SUPERSEDES the earlier "all large chips are right" report, see below
'D1': -90, 'D4': -90, 'D5': -90, 'U12': -90, # SOT-23-6, reconstructed hypothesis
'U1': -180, # SOT-23-5, confirmed (two -90 corrections)
'U4': -90, # SOT-23-5, confirmed ("U4 is good")
'Q1': 180, 'Q2': 180, # SOT-23 bottom layer, confirmed "upside down"
'D2': -90, # custom footprint, confirmed "90 CW"
'D3': 180, # SMA diode, confirmed "180"
'C65': 180, # electrolytic cap, confirmed "180"
'U2': -90, # SOT-583-8, confirmed "90 CW"
'U3': 180, # custom SOT95P280X110-6N footprint, confirmed "180"
} # positive = CCW, negative = CW
with open('re-bba-rb-cpl.csv', newline='') as f:
rows = list(csv.DictReader(f))
for r in rows:
@@ -50,6 +70,9 @@ with open('re-bba-rb-cpl.csv', 'w', newline='') as f:
writer.writerows(rows)
```
If a new correction comes in from a placement-preview check, add it to
*this* dict (and the table below), never work from a hand-copied subset.
When regenerating the CPL from scratch (e.g. after a reroute or component
move), **re-run `kicad-cli pcb export pos` for fresh positions, then
reapply every correction below** — don't just diff/copy the old file, since
@@ -58,10 +81,27 @@ correction offset applied on top.
## Confirmed correct as-is — apply NO correction
- **U8, U11 (LQFP-48/64)**, **U9 (QFN-48)** — "all large chips are right"
(user, direct placement-preview check). Raw KiCad rotation is correct.
- **U4 (SOT-23-5)** — confirmed good *after* the -90° family correction
below was applied (net rotation 270°, i.e. raw 0° − 90°).
**These are the only parts that take zero correction.** Everything else in
this section title's spirit but requiring a nonzero offset (like U4 below)
lives in the corrections table, not here — filing U4 in this section
previously (saying "confirmed good" without also flagging its required -90°
delta) caused a real bug: a later reapplication pass built its correction
dict from this section's prose and silently skipped U4, regenerating the
CPL with U4 back at raw/wrong rotation. Don't repeat that — if a part needs
*any* nonzero delta from raw, it belongs in the table below, full stop, even
if that delta is "confirmed correct and needs no further correction beyond
it."
- **U8 (LQFP-48)**, **U9 (QFN-48)** — "all large chips are right" (user,
direct placement-preview check). ⚠️ **That single report also covered U11,
and U11 later turned out to need −90° after all** (direct check,
2026-07-31). So the "large chips are fine" observation is now known to be
wrong for at least one of the three parts it covered, and U8/U9 rest
entirely on that same weakened report. Treat both as **unverified**, not
settled — re-check them in the placement preview before assembly. Do not
cite "all large chips are right" as evidence again.
- **D8, D9 (LED_0603, bottom layer)** — verified 2026-07-31 by tracing the
circuit rather than by eye, see "D8/D9 polarity" below. No correction.
- **J2 (HR911105A magjack, rot=90° in the PCB file)** — not a CPL-rotation
question (J2 doesn't need per-part correction below, it's not in the CPL
correction set), but its physical orientation was independently verified:
@@ -77,13 +117,16 @@ Each row: designator, package, raw→corrected, confidence.
| Ref | Package | Raw | Corrected | Confidence |
|---|---|---|---|---|
| U7 | SOIC-8 | 90° | **180°** | Reconstructed hypothesis (see below) — not independently re-confirmed |
| U10 | SOIC-8 | 0° | **90°** | Reconstructed hypothesis — not independently re-confirmed |
| U7 | SOIC-8 | 90° | **0°** (net: +90° reconstructed hypothesis, then +180° more, user-confirmed 2026-07-31) | **Confirmed.** Note this landed on exactly the same net correction as U10 (+270°), which retroactively makes the two SOIC-8 parts consistent — the original bare "+90°" hypothesis was wrong for *both*, in the same direction and by the same amount |
| U11 | LQFP-64 | -90° | **180°** | **Confirmed** ("90 degrees clockwise", 2026-07-31). Previously filed as needing NO correction on the strength of "all large chips are right" — that report was wrong for this part. See the note in the no-correction section above: U8/U9 inherit the doubt |
| U10 | SOIC-8 | 0° | **270°** (net: +90° reconstructed hypothesis, then +180° more, user-confirmed) | Partially confirmed — the +90° hypothesis alone was WRONG/incomplete (needed another 180° on top). **This means the SOIC "+90°" hypothesis should not be trusted for U7 either** without its own direct check, since it's now proven wrong at least once. |
| U3 | custom `SOT95P280X110-6N` | 0° | **180°** | **Confirmed** ("180°") |
| D1 | SOT-23-6 | 0° | **270°** | Reconstructed hypothesis — not independently re-confirmed |
| D4 | SOT-23-6 | 180° | **90°** | Reconstructed hypothesis — not independently re-confirmed |
| D5 | SOT-23-6 | 180° | **90°** | Reconstructed hypothesis — not independently re-confirmed |
| U12 | SOT-23-6 | 180° | **90°** | Reconstructed hypothesis — not independently re-confirmed |
| U1 | SOT-23-5 | 180° | **0°** (two corrections: -90° then another -90°, user-confirmed both times) | **Confirmed** by direct user feedback, twice |
| U4 | SOT-23-5 | 0° | **270°** (-90°, the same family correction as D1/D4/D5/U12) | **Confirmed** — user checked and said "U4 is good" after this delta, no second correction needed (unlike U1) |
| Q1 | SOT-23 (bottom layer) | -90° | **90°** | **Confirmed** ("upside down" = 180°, direction-agnostic) |
| Q2 | SOT-23 (bottom layer) | -90° | **90°** | **Confirmed** (same as Q1) |
| D2 | custom `SON50P110X213X50-7` | 0° | **270°** | **Confirmed** ("90° clockwise") |
@@ -105,14 +148,55 @@ SOT-23-5, both got the -90° family correction, but U1 needed a *second*
hypothesis" row above as **worth a fresh placement-preview check**, not
settled fact, despite no contradicting feedback having come in since.
## D8/D9 polarity — checked by circuit tracing, NOT by eye (2026-07-31)
D8 was reported as *possibly* upside down because "it connects with its
negative side to Q1". **That observation is correct behaviour, not a
fault** — D8's cathode is *supposed* to face Q1. Tracing the net:
```
D8: 3V3 → R41 → D8.pad2 (A) ─ D8.pad1 (K) → Q1.pad3 (C) → Q1.pad2 (E) → GND
Q1 is an NPN low-side switch, base Q1.pad1 ← R39.
Current can only flow if the LED cathode is the Q1 end. ✔
D9: 3V3 → Q2.pad2 (E) → Q2.pad3 (C) → R42 → D9.pad2 (A) ─ D9.pad1 (K) → GND
Q2 is a PNP high-side switch, base Q2.pad1 ← R40.
D9's cathode goes straight to GND; it does NOT touch Q2 directly. ✔
```
Both are `LED_SMD:LED_0603_1608Metric` on **B.Cu**, both at raw −90°, and
both have pad 1 = cathode (the footprint's B.Fab chamfer marks the pad-1 /
cathode end). Absolute pad geometry, with the back-layer X-mirror applied:
| | pad 1 (K) | pad 2 (A) | anode's partner |
|---|---|---|---|
| D8 | (167.420, **47.300**) | (167.420, **48.875**) | R41 pad 2 at (166.170, 48.875) |
| D9 | (164.940, **47.340**) | (164.940, **48.915**) | R42 pad 2 at (163.690, 48.917) |
The anode pads land at the *same Y* as their series resistor's pad — that
alignment is what confirms the back-layer mirror was applied correctly when
computing these (get the mirror wrong and pad 1/2 swap, inverting the whole
conclusion). Q1's collector pad sits at (165.350, 45.580), i.e. **above** D8
in Y — the same side as D8's cathode. So "cathode faces Q1" is exactly right.
**Both D8 and D9 are oriented identically** (cathode toward smaller Y). That
is a useful invariant: they are the same part in the same circuit role, so if
a future preview shows one of them needing a flip, *both* need it — a
correction applied to only one of the pair is a mistake.
Note this relationship is **mirror-invariant**: whether the assembler renders
the bottom layer viewed-from-below or seen-through-the-board, "D8's cathode
end is the end nearer Q1" stays true. So it is a safe thing to eyeball in a
preview, unlike absolute left/right or up/down judgements on bottom-layer
parts.
## Parts never checked at all
Every 0402/0603/0805 passive (R/C/L), J1/J3/J4 connectors, the custom
`U3` footprint (`hardware:SOT95P280X110-6N`), and anything else not listed
above is sitting at **raw, unverified KiCad rotation** in the CPL. Passives
in symmetric packages are usually fine raw (this matched observed behavior
for the ones implicitly checked), but this has not been confirmed
part-by-part the way the table above was.
Every 0402/0603/0805 passive (R/C/L) except C65, J1/J3/J4 connectors, and
anything else not listed in the corrections table above is sitting at
**raw, unverified KiCad rotation** in the CPL. Passives in symmetric
packages are usually fine raw (this matched observed behavior for the ones
implicitly checked), but this has not been confirmed part-by-part the way
the table above was.
## Bottom line for whoever picks this up next
hardware/re-bba-rb/Fpga.kicad_sch
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(property "Reference" "#PWR0J4"
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hardware/re-bba-rb/REVIEW.md
+173 -8
View File
@@ -69,12 +69,34 @@ datasheet extraction, WebSearch/WebFetch for parts and reference designs.
earlier review note claiming they should be 1.8 V was wrong; do not "fix").
VREGIN=3V3, VREGOUT→VCORE (1.8 V) with 4.7 µF + 3×100 nF on pins 12/37/64;
4×VCCIO decoupled; REF = 12k 1 % to GND (DS requirement); RESET RC
(10k/100 nF); 12 MHz crystal Y1 (CL=12 pF part vs 18 pF caps — verified
consistent); TEST→GND, AGND→GND.
(10k/100 nF); 12 MHz crystal Y1 (CL=12 pF part vs 18 pF caps — re-verified
2026-07-31 against the real YXC datasheet + LCSC page; correct, do not
change); TEST→GND, AGND→GND.
- **EEPROM 93LC46B (U7)**: interface **was wrong** (DO+DI both direct to
EEDATA) → fixed per DS Table 3.4: EE_DO net, R30 2.2k (C25879) to EE_DATA,
R31 10k (C25744) pull-up to 3V3, DI direct. 93LC46B = fixed 16-bit org =
correct for FT2232H. Verified in netlist.
- **EE_CS pull-down (R43, 10 kΩ) — ADDED 2026-07-31.** FT2232H DS Table 3.4
states EECS/EECLK/EEDATA are all **"Tri-State during device reset"**, so CS
floats while the FT2232H is in reset. The Microchip 93LC46B DS is explicit:
*"an external 10 kΩ pull-down protection resistor should be added to the CS
pin"*, and **CS is active-HIGH** (*"A high level selects the device; a low
level deselects the device and forces it into Standby mode"*). **It must be
a pull-DOWN — a pull-UP would hold the EEPROM permanently selected.** Netlist
verified: `EE_CS: R43.1, U7.1, U8.63`.
- **EE_CLK deliberately has NO pull resistor — do not add one.** With CS held
low the device is in Standby, and the 93LC46B DS states *"Before a Start
condition is detected, CS, CLK and DI may change in any combination…
without resulting in any device operation."* A floating clock is harmless
once CS is pulled down. (A reviewer suggested pull-ups on both EE_CLK and
EE_CS; only the CS pull-DOWN is correct.)
- **FT2232H oscillator needs no RExt / no external feedback resistor —
settled, do not add one.** DS Figure 6.5 shows crystal + 2 caps only; FTDI
publishes **no gm, no drive-level and no negative-resistance figure**, so a
drive resistor cannot be sized from their data and their reference does not
use one (feedback is internal). This is a genuine architectural difference
from the W5100S, which explicitly has *no* internal feedback resistor and
models RExt in its Figure 23. Y1 caps stay 18 pF (CL=12 pF part).
- **FTDI↔flash/FPGA config pins**: **rewired 2026-07-18** to stock iceprog
convention: SCK=ADBUS0, MOSI=ADBUS1, MISO=ADBUS2, FLASH_CS=ADBUS4,
CDONE=ADBUS6, CRESET=ADBUS7 (verified against iceprog.c; old ADBUS3/ACBUS0/
@@ -116,8 +138,78 @@ datasheet extraction, WebSearch/WebFetch for parts and reference designs.
itself uses 12k+300R; 0.8 % immaterial). Closed.
- **Crystal Y2**: 25 MHz, CL=12 pF part (C9006) vs 18 pF caps → CL≈12 pF ✓
(DS Table 9 wants 12 pF); mandatory external 1 MΩ feedback (R17) present ✓
(DS: "W5100S has no feedback resistor"). FTDI ref-note: no series RExt
(ref uses 0 Ω) — accepted.
(DS: "W5100S has no feedback resistor"). **The caps are CORRECT: both
crystals are CL = 12 pF, and `CL = C/2 + Cstray` → 18 pF caps deliver
exactly 12 pF. An attempt on 2026-07-31 to "fix" the caps to 30 pF/10 pF
was a regression against this reviewed item and has been reverted. Do not
change the crystal caps.** The trigger for that mistake was wrong `CL`
metadata in the schematic symbol properties (Y1 said 18 pF, Y2 said 8 pF) —
those properties have now been corrected to match the parts (see below).
⚠️ **Where the CL = 12 pF figure actually comes from — read this before
"re-verifying" it.** It is NOT in `datasheets/Ysx321SL.pdf`. That is the
generic YSX321SL *series* datasheet and its Load Capacitance row reads
**"10pF, 20pF, or specify"** — so opening it and looking for 12 pF gives
the alarming impression that the fitted caps are wrong for either standard
option. These two parts are the "or specify" variants, and CL is fixed by
the **ordering code**, confirmed on the LCSC part pages (re-confirmed
2026-07-31):
- Y1 `X322512MOB4SI` (**C70565**): 12 MHz, **CL 12 pF**, ±10 ppm, ESR 80 Ω
- Y2 `X322525MOB4SI` (**C9006**): 25 MHz, **CL 12 pF**, ±10 ppm, ESR 50 Ω
Everything else in the series datasheet *does* corroborate the review
numbers used elsewhere in this file: C0 = 3 pF max, DL = 200 µW max
(100 µW typ — the basis for the R44 RExt decision), and the ESR bands
(12–15 MHz → 80 Ω, 16–31 MHz → 50 Ω). Only CL needs the part page.
**The common way to get this wrong** is to apply `C = 2 × CL` = 24 pF and
conclude 18 pF is too small. That omits stray capacitance. The correct
form is `C = 2 × (CL − Cstray)` = 2 × (12 − 3) = **18 pF**, where Cstray
(PCB trace + oscillator pin capacitance) is ~3 pF. If a reviewer says the
caps are low, check whether they subtracted Cstray before re-opening this.
**Residual sensitivity (the real uncertainty, and it is acceptable):** the
match is exact only if Cstray is exactly 3 pF; the realistic range is
2–5 pF, giving CL_actual 11–14 pF against the rated 12 pF. Pulling with
C0 = 3 pF and motional C1 ≈ 6 fF works out to roughly **+14 ppm to
−24 ppm**. Against 100BASE-TX's ±100 ppm requirement on the 25 MHz
reference, the worst-case stack (±10 tolerance + ±20 temp + ±3/yr aging +
±24 load) is ~±60 ppm — inside spec with margin. For Y1 the FT2232H's USB
budget (±500 ppm high-speed, ±2500 ppm full-speed) is met by a wide
margin. No change warranted; measure at bring-up if convenient.
- **RExt on XTAL_O (R44, 49.9 Ω) — ADDED 2026-07-31, reverses the earlier
"no series RExt (ref uses 0 Ω) — accepted" decision.** New evidence that
was not available at the original review: the crystal datasheet only
entered the repo on 2026-07-31 and rates the part at **DL = 200 µW max**
(100 µW typ), whereas W5100S Table 9 tells you to select a crystal rated
**500 µW** — i.e. the fitted crystal can be overdriven ~2.5× by the chip.
RExt is the datasheet's own prescribed remedy ("RExt: Resistor for
limiting the drive level (DL)… Excess power can destroy the crystal") and
is modelled in DS Figure 23. Topology follows Figure 23 exactly — RF
(R17) across the **chip pins** XSCI↔XSCO, RExt between XSCO and the
crystal/CL2 node; this required splitting the old XTAL_O net, so U11 pin 11
now sits on a new **XSCO** net:
XTAL_I : C62(CL1), R17(RF), U11.12, Y2.1
XSCO : R17(RF), R44(RExt), U11.11
XTAL_O : C63(CL2), R44(RExt), Y2.3
Value 49.9 Ω chosen from the DS gain-margin formula with the REAL specs
(F=25 MHz, ESR=50 Ω per the 16–31 MHz band, C0=3 pF max, CL=12 pF,
gm=16.7 mA/V): **margin 7.53×**, against a DS requirement of ≥5 (the
"6.99 dB" in Table 8 is 10·log₁₀5). **Ceiling is 100 Ω** — 120 Ω already
fails the startup spec. Fitted value is a starting point; part fields are
intentionally blank so it is re-selected/confirmed at bring-up by
measuring drive level.
- **Crystal symbol properties corrected 2026-07-31** (they were metadata-only
errors, no copper impact, but they caused the regression above):
Y1 CL 18 pF→**12 pF**, ESR 50 Ω→**80 Ω** (DS band 12–15 MHz),
tol ±30 ppm→**±10 ppm**; Y2 CL 8 pF→**12 pF**, C0 7 pF→**3 pF**,
ESR 30 Ω→**50 Ω** (band 16–31 MHz), tol ±50 ppm→**±10 ppm**.
- **Known deviation, accepted**: W5100S DS **Table 8 specifies a CL = 8 pF
crystal** (revision history logs "Modified Load capacitance value
(12p → 8p)"), while **Table 9 still says 12 pF** and was never updated.
The fitted part is 12 pF, matching Table 9. Frequency accuracy is
unaffected (the crystal sees exactly its rated load, so no pulling error);
the only cost is gain margin, which is 7.75× with R44 — well clear of the
≥5 requirement. Accepted; do not re-flag without bench evidence.
- **MDI section — now implements the WIZnet ref schematic item-for-item**:
49.9 Ω×4 (R26–R29, C25120) + 100 nF×2 (C18/C19) termination on the PHY-side
nets; 3.3 Ω×4 series dampers (R32–R35, C137986) — chain per line:
@@ -164,10 +256,83 @@ datasheet extraction, WebSearch/WebFetch for parts and reference designs.
rated for 3.3 V lines. Note: BOM part C49383400 is the **ElecSuper clone**
("(ES)"), pin-compatible — bring-up suspect only if ESD behaviour odd.
- **EXTIN**: 10k (R18) to **SP1_3V3 (the GC's own rail)** — correct, doesn't
back-power. **12 V**: J3.5 → 12V_EXI (power tree). J3.8 (second 3.3 V pin)
deliberately NC. Series elements: R24 100 Ω on EXI_CLK (input damping),
R21/R25 as above. INT (J3.3) driven by FPGA pin 46 — gateware should use
open-drain emulation (TODO).
back-power. **12 V**: J3.5 → **12V_RAW → U13 eFuse → 12V_EXI** (see next
bullet; was a straight J3.5→12V_EXI connection before 2026-07-31). J3.8
(second 3.3 V pin) deliberately NC. Series elements: R24 100 Ω on EXI_CLK
(input damping), R21/R25 as above. INT (J3.3) driven by FPGA pin 46 —
gateware should use open-drain emulation (TODO).
- **12 V inrush limiter (U13, TPS25961 eFuse) — ADDED 2026-07-31** to protect
the GameCube's 12 V supply from the surge charging C65+C3+C4+C6 (**120 µF**)
at plug-in/power-on. Topology (netlist-verified):
12V_RAW : J3.5, D3(TVS), C66(Cin 100nF), R46, U13.6 IN
12V_EXI : U13.1 OUT, C65, C3, C4, C6, U3.3 VIN, U3.5 EN
EFUSE_EN : R46, R47, U13.5 EN/UVLO
EFUSE_ILIM: R45, U13.3 ILIM
GND : U13.2 OVLO, U13.4 GND, R45.2, R47.2, C66.2
**D3 (SMAJ12A TVS) stays on the INPUT side on purpose** — it clamps
GC-side surges before they reach the eFuse's 21 V absolute maximum. **C65
is on the OUTPUT side on purpose** — it is the bulk cap whose inrush we are
rate-limiting; moving it upstream would defeat the whole circuit.
**U3 (buck) needed no change**: because the eFuse was inserted *upstream of
the existing 12V_EXI net name*, U3's VIN and EN both land on the switched
rail automatically.
- **Inrush is set by the device's INTERNAL slew rate, not an external cap.**
dV/dt = 5.17 V/ms (fixed, typical) ⇒ I = C·dV/dt = 120 µF × 5.17 V/ms =
**621 mA** over a 2.3 ms ramp. R_ILIM only matters if it is set *below*
that figure.
- **R45 = 100 kΩ ⇒ I_LIM ≈ 500 mA** (datasheet Equation 6: R_ILIM =
50000/I_LIM; 100 kΩ is one of TI's own characterised points, 0.516 A typ,
±18% ⇒ 0.42–0.61 A). This both caps inrush at 500 mA and gives **3.8×
headroom** over the ~130 mA steady-state 12 V draw. 100 kΩ is deliberately
inside a valid ON-resistance bin — **Table 7-1 forbids 58.8–66.7 kΩ,
111–142 kΩ and 250–500 kΩ**; do not "round" R45 into those bands.
- **Startup dissipation is safe**: FET energy = ½CV² = **8.65 mJ** regardless
of ramp rate ⇒ ~3.0 W average over 2.9 ms. Figure 6-31 puts time-to-thermal-
shutdown at ~3 W far beyond 100 ms. Steady-state loss is 106 mΩ × 0.13² =
**1.8 mW**, negligible.
- **R46/R47 = 620 k/100 k ⇒ UVLO on at 8.9 V typ (9.2 V worst case), off at
8.2 V**, 16.7 µA leakage. **This is deliberately well below 12 V — do not
"improve" it upward.** Two reasons: (a) the EN/UVLO threshold is specified
1.2–1.28 V, so an ~11.4 V setting has a worst case of 11.78 V and could
refuse to start on a healthy console once PSU tolerance is added; (b) more
importantly the falling threshold scales with it (91% of rising), and the
eFuse pulls 500 mA during the 2.9 ms ramp — at a ~11 V setting a source
impedance of only ~1.2 Ω would sag the rail below drop-out mid-ramp,
causing retry oscillation that may never complete startup. The 620 k/100 k
setting tolerates **3.85 V of sag**. If tighter supervision is ever wanted,
680 k/100 k (9.7 V on, 3.2 V sag margin) is the furthest to push it —
beyond that use an FPGA-read divider, not the eFuse enable.
- **OVLO tied directly to GND** = internal fixed OV threshold. Note the OVLO
pin's absolute maximum is only **6.5 V** — it must never see the 12 V rail.
- **Thermal pad must connect to the GND plane** (datasheet requirement); the
chosen footprint is the `_ThermalVias` variant for this reason.
- Symbol: no TPS25961 exists in the KiCad libraries (the stock `TPS2596xx`
is an 8-pin SO-8 with a different pinout — do not substitute it), so
`hardware/TPS25961.kicad_sym` was created and registered in
`sym-lib-table`. Footprint `Package_SON:WSON-6-1EP_2x2mm_P0.65mm_EP1x1.6mm_ThermalVias`.
- **EXI series-resistor assignment — VERIFIED AGAIN 2026-07-31 against the
netlist + gateware pin directions, do not swap.** The DO/DI fix above moved
the *driven* line from J3.6 to J3.9, and the R21/R25 identities were swapped
to follow it. Confirmed live:
EXI_MISO : U9.3 (synth.py dir="o", FPGA drives) -> R25 33 Ω -> J3.9 (DI)
EXI_MOSI : J3.6 (DO, GC drives) -> R21 22 Ω -> U9.4 (dir="i", FPGA rx)
**33 Ω belongs on MISO** because that is the only line this board drives, so
it is genuine source termination (33 Ω + ~30 Ω iCE40 output ≈ 60 Ω into a
~50 Ω trace — mildly over-damped, the safe direction for EMI on a short
run). **22 Ω belongs on MOSI**, where the GC is the driver at the far side
of a connector we do not control; source termination is impossible there, so
the resistor only limits clamp current and damps at the receiver, a role
where the exact value matters much less. Swapping them would under-terminate
the one line we actually drive. This is the exact trap a future reader may
fall into after seeing the console-perspective DO/DI naming — the values
are already on the correct lines.
- **CS deliberately has NO series resistor — known asymmetry, not an
oversight.** All three of EXI_CLK, EXI_MOSI and EXI_CS are GC-driven inputs,
but only CLK (R24 100 Ω) and MOSI (R21 22 Ω) carry damping; J3.10 goes
straight to U9.45. CS is essentially static within a transaction (it frames
the transfer rather than toggling per bit), so receiver ringing matters far
less than on the clock or data lines. Recorded so it is not "fixed" on the
assumption it was forgotten; add one only if bring-up shows CS-edge noise.
- **J3 footprint provenance**: 12 contacts, 1 mm effective pitch, two
staggered depth rows, **front side only**, fingers to the board edge (the
`.kicad_dru` has a J3 edge-clearance exception for this). Geometry comes
hardware/re-bba-rb/TODO.md
+52 -4
View File
@@ -206,6 +206,30 @@ Major work this session:
at (148.49, 61.7225) near U11 pin 48. Verified 2026-07-22: nets
`/ethernet/ETH_RST` + `/ethernet/ETH_3V3` both present on the footprint,
0 unconnected items.
- [ ] **12 V inrush limiter (U13 TPS25961 eFuse) — SCHEMATIC DONE 2026-07-31**,
full design rationale in REVIEW.md §6. J3.5 → 12V_RAW → U13 → 12V_EXI;
D3 (TVS) stays upstream, C65 downstream. R45 100 k sets I_LIM ≈ 500 mA
(caps inrush, 3.8× the ~130 mA steady-state load); R46/R47 620 k/100 k
set UVLO ≈ 8.9 V; C66 100 nF is Cin. U13 = TPS25961DRVR, **LCSC
C5571272**.
- [ ] **PCB: place + route U13, R45, R46, R47, C66.** Two datasheet
requirements to honour in layout: (1) the **thermal pad must
connect to the GND plane** — the footprint is the `_ThermalVias`
variant, confirm the vias actually reach In1/In2 GND; (2) **OVLO
absolute max is 6.5 V** and it is tied to GND for the internal
fixed threshold — that connection must be solid and must never
see 12 V. Keep C66 close to U13's IN pin.
- [ ] **Select parts for R45 (100 k), R46 (620 k), R47 (100 k), C66
(100 nF)** — fields intentionally left blank. R45/R47 can reuse
the UNI-ROYAL 100 k C25741 already used by R4 (NOT C60490 - that part
is 10 k, an earlier note in this file had it wrong).
**Do not round R45 into 58.8–66.7 kΩ, 111–142 kΩ or 250–500 kΩ**
(datasheet Table 7-1 forbidden ON-resistance bins).
- [ ] **Bench: verify inrush at GC power-on** — expect ≈500 mA for
~2.9 ms (was ~621 mA slew-limited, unbounded before the eFuse).
Also confirm no retry/motorboating at startup; if the rail sags
more than expected, that points at SP1 connector/cable impedance,
not the UVLO setting.
- [ ] **Gateware: gate all outputs on GC_ON** — when GC_ON=0 the W5100S is
unpowered (U12) and the GC is off, but FPGA banks stay at 3.3 V. Hold
the W5100S bus and EXI outputs Hi-Z/low to avoid back-powering.
@@ -327,10 +351,21 @@ Major work this session:
WIZnet's own reference synthesizes it as 12 k + 300 Ω. The 0.8 %
deviation on a bandgap bias resistor is immaterial (well under the
combined tolerance of the ref design's two 1 % parts).
- [x] Crystals Y1/Y2 — VERIFIED 2026-07-17: the BOM parts are both CL = 12 pF
(Y1 YXC X322512MOB4SI / C70565, Y2 X322525MOB4SI / C9006, both JLC
Basic, ±10 ppm) — correct for the 18 pF load caps and the W5100S
Table 9 recommendation. No change needed.
- [x] Crystals Y1/Y2 — VERIFIED 2026-07-17, **RE-CONFIRMED 2026-07-31**: the
BOM parts are both CL = 12 pF (Y1 YXC X322512MOB4SI / C70565,
Y2 X322525MOB4SI / C9006, both JLC Basic, ±10 ppm) — correct for the
18 pF load caps (`CL = C/2 + Cstray` → 18/2 + 3 = 12 pF exactly).
**This entry was right; a 2026-07-31 attempt to change the caps to
30 pF/10 pF was a regression and has been reverted.** The cause was
wrong `CL` metadata in the schematic symbol properties (Y1 said 18 pF,
Y2 said 8 pF) — properties are now corrected to the real specs from
`datasheets/Ysx321SL.pdf`. Do not change the crystal caps.
Note: the "W5100S Table 9 recommendation" citation above is fragile —
Table 9 says 12 pF but **Table 8 says 8 pF**, and the DS revision
history logs "Modified Load capacitance value (12p → 8p)". The fitted
12 pF part therefore matches the *stale* table. Accepted as a
documented deviation (frequency accuracy unaffected; gain margin 7.75×
with R44) — see REVIEW.md §5.
- [x] 12 V-rail parts ≥ 25 V — VERIFIED in BOM audit 2026-07-17: C3/C4 25 V,
C6 50 V, C65 25 V (Lelon SMD electrolytic); D3 SMAJ12A correct.
- [x] 1 % tolerance — VERIFIED in BOM audit 2026-07-17: R1/R2, R3/R4, R10,
@@ -346,6 +381,19 @@ Major work this session:
separates chassis via 1 nF/2 kV — acceptable choice, confirm intent).
- [ ] Confirm at bring-up (from CLAUDE.md): W5100S register addresses / MR
bits were written from memory.
- [ ] **Measure Y2 crystal drive level at bring-up and tune R44 (RExt).**
Added 2026-07-31 at **49.9 Ω** (gain margin 7.53×, DS requires ≥5;
**ceiling 100 Ω**, 120 Ω fails startup). Reason it exists: the fitted
crystal is rated **DL = 200 µW max** but W5100S Table 9 says select a
**500 µW** part, so the chip can overdrive it ~2.5×. Part fields are
deliberately blank — confirm the value on the bench (scope the crystal,
compute DL) before committing a BOM line. If drive is comfortably under
200 µW a smaller value (or 0 Ω, per the WIZnet reference) is fine; if
it's high, go up but stay ≤100 Ω. See REVIEW.md §5.
- [ ] **Select a part for R43** (EE_CS 10 kΩ pull-down, added 2026-07-31).
Any 10 kΩ 0402 works — the in-stock YAGEO RC0402FR-0710KL / C60490
already used on R2/R5/R18/R31/R36 is the obvious choice; fields were
left blank so it doesn't silently inherit an out-of-stock part.
## JLCPCB ordering notes (DRC clean — these are order-form options)
hardware/re-bba-rb/Usb Connector.kicad_sch
+238 -66
View File
@@ -4952,6 +4952,16 @@
)
(uuid "88b43752-c3ef-4728-b5c9-2bcb2a4ac66f")
)
(wire
(pts
(xy 215.9 209.55) (xy 215.9 212.09)
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(stroke
(width 0)
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(uuid "8a7a2236-e5d2-455b-adb6-d5a9c822f7a0")
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(wire
(pts
(xy 233.68 66.04) (xy 233.68 74.93)
@@ -5152,6 +5162,16 @@
)
(uuid "a695a9ab-d6ab-46b5-a6bd-543dc98c2cdf")
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(wire
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(wire
(pts
(xy 236.22 187.96) (xy 238.76 187.96)
@@ -5542,6 +5562,16 @@
)
(uuid "007729b4-9e2e-40dc-bc45-0e669579a602")
)
(label "EE_CS"
(at 215.9 199.39 90)
(effects
(font
(size 1.27 1.27)
)
(justify left bottom)
)
(uuid "030b4ce2-523f-44c0-9f6f-0459351b45e2")
)
(label "FT_DN"
(at 213.36 107.95 180)
(effects
@@ -6465,6 +6495,83 @@
)
)
)
(symbol
(lib_id "power:GND")
(at 215.9 212.09 0)
(unit 1)
(body_style 1)
(exclude_from_sim no)
(in_bom yes)
(on_board yes)
(in_pos_files yes)
(dnp no)
(uuid "086e6392-c7bb-4f02-965b-e94f550e4c1f")
(property "Reference" "#PWR016"
(at 215.9 215.9 0)
(hide yes)
(show_name no)
(do_not_autoplace no)
(effects
(font
(size 1.27 1.27)
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(property "Value" "GND"
(at 215.9 214.376 0)
(show_name no)
(do_not_autoplace no)
(effects
(font
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(property "Footprint" ""
(at 215.9 212.09 0)
(hide yes)
(show_name no)
(do_not_autoplace no)
(effects
(font
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(property "Datasheet" ""
(at 215.9 212.09 0)
(hide yes)
(show_name no)
(do_not_autoplace no)
(effects
(font
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(property "Description" "Power symbol creates a global label with name \"GND\" , ground"
(at 215.9 212.09 0)
(hide yes)
(show_name no)
(do_not_autoplace no)
(effects
(font
(size 1.27 1.27)
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(pin "1"
(uuid "7f0ff9e1-3057-429e-b1df-10cbe600e560")
)
(instances
(project "re-bba-rb"
(path "/dbb182a6-d579-468e-b98b-6f0950da9e3a/64033f5d-a512-44d7-9483-4c31ef84bd56"
(reference "#PWR016")
(unit 1)
)
)
)
)
(symbol
(lib_id "power:GND")
(at 233.68 232.41 0)
@@ -6867,12 +6974,6 @@
(uuid "196c5877-453e-40e1-a88d-b0467fa52e8f")
)
(instances
(project "usb"
(path "/11111111-2222-3333-4444-555555555555"
(reference "R21")
(unit 1)
)
)
(project "re-bba-rb"
(path "/dbb182a6-d579-468e-b98b-6f0950da9e3a/64033f5d-a512-44d7-9483-4c31ef84bd56"
(reference "R7")
@@ -7308,12 +7409,6 @@
(uuid "7060e50e-ca34-4d72-95ab-61cf7c8e037a")
)
(instances
(project "usb"
(path "/11111111-2222-3333-4444-555555555555"
(reference "D10")
(unit 1)
)
)
(project "re-bba-rb"
(path "/dbb182a6-d579-468e-b98b-6f0950da9e3a/64033f5d-a512-44d7-9483-4c31ef84bd56"
(reference "D1")
@@ -7549,12 +7644,6 @@
(uuid "a1ef86c5-d111-4afd-87d0-09f81da53010")
)
(instances
(project "usb"
(path "/11111111-2222-3333-4444-555555555555"
(reference "J10")
(unit 1)
)
)
(project "re-bba-rb"
(path "/dbb182a6-d579-468e-b98b-6f0950da9e3a/64033f5d-a512-44d7-9483-4c31ef84bd56"
(reference "J1")
@@ -8524,12 +8613,6 @@
(uuid "91b76037-3761-4d59-a622-0d4c0b5e4b27")
)
(instances
(project "usb"
(path "/11111111-2222-3333-4444-555555555555"
(reference "FB2")
(unit 1)
)
)
(project "re-bba-rb"
(path "/dbb182a6-d579-468e-b98b-6f0950da9e3a/64033f5d-a512-44d7-9483-4c31ef84bd56"
(reference "FB1")
@@ -8808,12 +8891,6 @@
(uuid "4ff88084-1b2c-4892-824e-4dd38b3b65ce")
)
(instances
(project "usb"
(path "/11111111-2222-3333-4444-555555555555"
(reference "R20")
(unit 1)
)
)
(project "re-bba-rb"
(path "/dbb182a6-d579-468e-b98b-6f0950da9e3a/64033f5d-a512-44d7-9483-4c31ef84bd56"
(reference "R6")
@@ -9304,12 +9381,6 @@
(uuid "2e03932d-a5c1-4bf2-ac90-bf1f3e837cee")
)
(instances
(project "usb"
(path "/11111111-2222-3333-4444-555555555555"
(reference "C40")
(unit 1)
)
)
(project "re-bba-rb"
(path "/dbb182a6-d579-468e-b98b-6f0950da9e3a/64033f5d-a512-44d7-9483-4c31ef84bd56"
(reference "C25")
@@ -9600,12 +9671,6 @@
(uuid "da5d2cc4-5f12-4dc1-a77d-2fcb44baece9")
)
(instances
(project "usb"
(path "/11111111-2222-3333-4444-555555555555"
(reference "C41")
(unit 1)
)
)
(project "re-bba-rb"
(path "/dbb182a6-d579-468e-b98b-6f0950da9e3a/64033f5d-a512-44d7-9483-4c31ef84bd56"
(reference "C26")
@@ -10918,7 +10983,7 @@
)
)
)
(property "ESR" "50R"
(property "ESR" "80R"
(at 204.47 166.37 0)
(hide yes)
(show_name no)
@@ -10929,7 +10994,7 @@
)
)
)
(property "Tolerance" "±30ppm"
(property "Tolerance" "±10ppm"
(at 204.47 166.37 0)
(hide yes)
(show_name no)
@@ -10940,7 +11005,7 @@
)
)
)
(property "CL" "18pF"
(property "CL" "12pF"
(at 204.47 166.37 0)
(hide yes)
(show_name no)
@@ -10986,12 +11051,6 @@
(uuid "f0b6444c-d6b5-4bec-b637-ad63533ceaca")
)
(instances
(project "usb"
(path "/11111111-2222-3333-4444-555555555555"
(reference "Y10")
(unit 1)
)
)
(project "re-bba-rb"
(path "/dbb182a6-d579-468e-b98b-6f0950da9e3a/64033f5d-a512-44d7-9483-4c31ef84bd56"
(reference "Y1")
@@ -11798,7 +11857,7 @@
)
)
)
(property "MPN" "RC0402FR-0710KL"
(property "MPN" "0402WGF1002TCE"
(at -77.47 -77.47 0)
(hide yes)
(show_name no)
@@ -11809,7 +11868,7 @@
)
)
)
(property "Manufacturer" "YAGEO"
(property "Manufacturer" "UNI-ROYAL"
(at -77.47 -77.47 0)
(hide yes)
(show_name no)
@@ -11820,7 +11879,7 @@
)
)
)
(property "LCSC" "C60490"
(property "LCSC" "C25744"
(at -77.47 -77.47 0)
(hide yes)
(show_name no)
@@ -12280,12 +12339,6 @@
(uuid "74749c44-aa65-49a4-9314-1434a536fff4")
)
(instances
(project "usb"
(path "/11111111-2222-3333-4444-555555555555"
(reference "U30")
(unit 1)
)
)
(project "re-bba-rb"
(path "/dbb182a6-d579-468e-b98b-6f0950da9e3a/64033f5d-a512-44d7-9483-4c31ef84bd56"
(reference "U8")
@@ -12294,6 +12347,131 @@
)
)
)
(symbol
(lib_id "Device:R")
(at 215.9 205.74 0)
(unit 1)
(body_style 1)
(exclude_from_sim no)
(in_bom yes)
(on_board yes)
(in_pos_files yes)
(dnp no)
(uuid "d7813bb0-0c2e-4dcb-8ebb-3c96f38c371f")
(property "Reference" "R43"
(at 217.932 203.835 0)
(show_name no)
(do_not_autoplace no)
(effects
(font
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(justify left)
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(property "Value" "10k"
(at 217.932 206.375 0)
(show_name no)
(do_not_autoplace no)
(effects
(font
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(property "Footprint" "Resistor_SMD:R_0402_1005Metric_Pad0.72x0.64mm_HandSolder"
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(do_not_autoplace no)
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(do_not_autoplace no)
(effects
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(property "Manufacturer" "UNI-ROYAL"
(at -77.47 -77.47 0)
(hide yes)
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(do_not_autoplace no)
(effects
(font
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(property "LCSC" "C25744"
(at -77.47 -77.47 0)
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(do_not_autoplace no)
(effects
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(property "Tolerance" "1%"
(at -77.47 -77.47 0)
(hide yes)
(show_name no)
(do_not_autoplace no)
(effects
(font
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(pin "1"
(uuid "2f95d900-0a46-44a6-ae83-151758759cfd")
)
(pin "2"
(uuid "6b6aaa72-d6ca-448e-ace7-70a942addca5")
)
(instances
(project "re-bba-rb"
(path "/dbb182a6-d579-468e-b98b-6f0950da9e3a/64033f5d-a512-44d7-9483-4c31ef84bd56"
(reference "R43")
(unit 1)
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(symbol
(lib_id "Device:C")
(at 279.4 69.85 0)
@@ -12698,12 +12876,6 @@
(uuid "d297bf58-f344-4dd4-8895-b6cf566b1bdc")
)
(instances
(project "usb"
(path "/11111111-2222-3333-4444-555555555555"
(reference "FB1")
(unit 1)
)
)
(project "re-bba-rb"
(path "/dbb182a6-d579-468e-b98b-6f0950da9e3a/64033f5d-a512-44d7-9483-4c31ef84bd56"
(reference "FB2")
hardware/re-bba-rb/datasheets/Ysx321SL.pdf
LFS
BIN
View File
Binary file not shown.
hardware/re-bba-rb/datasheets/power/TPS25961.pdf
LFS
BIN
View File
Binary file not shown.
hardware/re-bba-rb/ethernet.kicad_sch
+153 -18
View File
@@ -7099,16 +7099,6 @@
)
(uuid "6cb58ee9-c975-4693-a5d8-62736a388ecb")
)
(wire
(pts
(xy 180.34 91.44) (xy 180.34 81.28)
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(stroke
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(uuid "6feac242-a9f5-40d0-b9c5-a34f891273cd")
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(wire
(pts
(xy 127 60.96) (xy 129.54 60.96)
@@ -8099,6 +8089,16 @@
)
(uuid "73b86046-bd3f-45cb-9e99-a97a34bc873d")
)
(label "XSCO"
(at 190.5 81.28 0)
(effects
(font
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(justify left bottom)
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(uuid "73c903da-05a3-4d01-ae02-cee17766a497")
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(label "ETH_TX_N"
(at 82.55 137.16 180)
(effects
@@ -8259,7 +8259,7 @@
)
(uuid "bbe71baf-6a71-4138-a182-77604917cb9b")
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(label "XTAL_O"
(label "XSCO"
(at 129.54 88.9 0)
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@@ -8369,6 +8369,16 @@
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(uuid "dc2ba5eb-bfc1-4ebc-8075-d0104b310e93")
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(label "XSCO"
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(uuid "e0383079-6182-4fea-a0fc-77b304202cc5")
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(label "ETH_3V3"
(at 228.6 123.19 90)
(effects
@@ -9415,7 +9425,7 @@
)
)
)
(property "MPN" "RC0402FR-0710KL"
(property "MPN" "0402WGF1002TCE"
(at 0 0 0)
(hide yes)
(show_name no)
@@ -9426,7 +9436,7 @@
)
)
)
(property "Manufacturer" "YAGEO"
(property "Manufacturer" "UNI-ROYAL"
(at 0 0 0)
(hide yes)
(show_name no)
@@ -9437,7 +9447,7 @@
)
)
)
(property "LCSC" "C60490"
(property "LCSC" "C25744"
(at 0 0 0)
(hide yes)
(show_name no)
@@ -13405,7 +13415,7 @@
)
)
)
(property "C0" "7pF"
(property "C0" "3pF"
(at 173.99 81.28 0)
(hide yes)
(show_name no)
@@ -13416,7 +13426,7 @@
)
)
)
(property "ESR" "30R"
(property "ESR" "50R"
(at 173.99 81.28 0)
(hide yes)
(show_name no)
@@ -13427,7 +13437,7 @@
)
)
)
(property "Tolerance" "±50ppm"
(property "Tolerance" "±10ppm"
(at 173.99 81.28 0)
(hide yes)
(show_name no)
@@ -13438,7 +13448,7 @@
)
)
)
(property "CL" "8pF"
(property "CL" "12pF"
(at 173.99 81.28 0)
(hide yes)
(show_name no)
@@ -13954,6 +13964,131 @@
)
)
)
(symbol
(lib_id "Device:R")
(at 186.69 81.28 90)
(unit 1)
(body_style 1)
(exclude_from_sim no)
(in_bom yes)
(on_board yes)
(in_pos_files yes)
(dnp no)
(uuid "a821398d-606e-427f-9d83-73f360f8f78b")
(property "Reference" "R44"
(at 186.69 78.74 0)
(show_name no)
(do_not_autoplace no)
(effects
(font
(size 1.27 1.27)
)
(justify left)
)
)
(property "Value" "49.9"
(at 186.69 83.82 0)
(show_name no)
(do_not_autoplace no)
(effects
(font
(size 1.27 1.27)
)
(justify left)
)
)
(property "Footprint" "Resistor_SMD:R_0402_1005Metric_Pad0.72x0.64mm_HandSolder"
(at 186.69 81.28 0)
(hide yes)
(show_name no)
(do_not_autoplace no)
(effects
(font
(size 1.27 1.27)
)
)
)
(property "Datasheet" ""
(at 186.69 81.28 0)
(hide yes)
(show_name no)
(do_not_autoplace no)
(effects
(font
(size 1.27 1.27)
)
)
)
(property "Description" "Resistor"
(at 186.69 81.28 0)
(hide yes)
(show_name no)
(do_not_autoplace no)
(effects
(font
(size 1.27 1.27)
)
)
)
(property "MPN" "0402WGF4999TCE"
(at 186.69 81.28 0)
(hide yes)
(show_name no)
(do_not_autoplace no)
(effects
(font
(size 1.27 1.27)
)
)
)
(property "Manufacturer" "UNI-ROYAL"
(at 186.69 81.28 0)
(hide yes)
(show_name no)
(do_not_autoplace no)
(effects
(font
(size 1.27 1.27)
)
)
)
(property "LCSC" "C25120"
(at 186.69 81.28 0)
(hide yes)
(show_name no)
(do_not_autoplace no)
(effects
(font
(size 1.27 1.27)
)
)
)
(property "Tolerance" "1%"
(at 186.69 81.28 0)
(hide yes)
(show_name no)
(do_not_autoplace no)
(effects
(font
(size 1.27 1.27)
)
)
)
(pin "1"
(uuid "6809dc1e-6a73-4278-a4c9-0dd310476713")
)
(pin "2"
(uuid "5f711664-ccf4-43d3-ba41-344f137f10c1")
)
(instances
(project "re-bba-rb"
(path "/dbb182a6-d579-468e-b98b-6f0950da9e3a/c2ddb95f-8a63-4bb0-b3f2-a27a372fea3a"
(reference "R44")
(unit 1)
)
)
)
)
(symbol
(lib_id "Device:C")
(at 236.22 129.54 0)
hardware/re-bba-rb/exi.kicad_sch
+1393 -126
View File
File diff suppressed because it is too large Load Diff
hardware/re-bba-rb/re-bba-rb.kicad_pcb
+11040 -7183
View File
File diff suppressed because it is too large Load Diff
hardware/re-bba-rb/re-bba-rb.kicad_pro
+283 -7
View File
@@ -159,7 +159,7 @@
"min_text_height": 0.8,
"min_text_thickness": 0.08,
"min_through_hole_diameter": 0.2,
"min_track_width": 0.2,
"min_track_width": 0.1,
"min_via_annular_width": 0.05,
"min_via_diameter": 0.3,
"solder_mask_to_copper_clearance": 0.0,
@@ -535,7 +535,7 @@
"microvia_drill": 0.1,
"name": "ETH_DP",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 3,
"priority": 5,
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.2,
"tuning_profile": "",
@@ -545,16 +545,34 @@
},
{
"bus_width": 12,
"clearance": 0.15,
"clearance": 0.25,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "FB_Sense",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 7,
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.15,
"tuning_profile": "",
"via_diameter": 0.6,
"via_drill": 0.3,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.15,
"diff_pair_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "LED",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 1,
"priority": 2,
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.15,
"tuning_profile": "",
@@ -572,7 +590,7 @@
"microvia_drill": 0.1,
"name": "Power",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 0,
"priority": 1,
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.3,
"tuning_profile": "",
@@ -590,7 +608,7 @@
"microvia_drill": 0.1,
"name": "PowerLV",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 1,
"priority": 3,
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.25,
"tuning_profile": "",
@@ -598,6 +616,40 @@
"via_drill": 0.3,
"wire_width": 6
},
{
"clearance": 0.1,
"diff_pair_gap": 0.25,
"diff_pair_width": 0.2,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Signal",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 0,
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.1,
"tuning_profile": "",
"via_diameter": 0.6,
"via_drill": 0.3
},
{
"bus_width": 12,
"clearance": 0.15,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Termination",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 6,
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.3,
"tuning_profile": "",
"via_diameter": 0.6,
"via_drill": 0.3,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.15,
@@ -608,7 +660,7 @@
"microvia_drill": 0.1,
"name": "USB_DP",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 2,
"priority": 4,
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.25,
"tuning_profile": "",
@@ -750,6 +802,230 @@
{
"netclass": "LED",
"pattern": "*Q2-C*"
},
{
"netclass": "Signal",
"pattern": "*ETH_A*"
},
{
"netclass": "Signal",
"pattern": "*ETH_D*"
},
{
"netclass": "Power",
"pattern": "/exi/EXI_GND"
},
{
"netclass": "Signal",
"pattern": "*ETH_RD*"
},
{
"netclass": "Signal",
"pattern": "*ETH_WR*"
},
{
"netclass": "Signal",
"pattern": "*RSET_BG*"
},
{
"netclass": "Signal",
"pattern": "*ETH_INT*"
},
{
"netclass": "Signal",
"pattern": "*ETH_RST*"
},
{
"netclass": "Signal",
"pattern": "*ETH_CS*"
},
{
"netclass": "Signal",
"pattern": "*LED_LNK*"
},
{
"netclass": "Signal",
"pattern": "*LED_ACT*"
},
{
"netclass": "Signal",
"pattern": "*FLASH_CS*"
},
{
"netclass": "Signal",
"pattern": "*FLASH_MISO*"
},
{
"netclass": "Signal",
"pattern": "*WP*"
},
{
"netclass": "Signal",
"pattern": "*FLASH_SCK*"
},
{
"netclass": "Signal",
"pattern": "*FLASH_MOSI*"
},
{
"netclass": "Signal",
"pattern": "*CRESET*"
},
{
"netclass": "Signal",
"pattern": "*UART_RXD*"
},
{
"netclass": "Signal",
"pattern": "*UART_TXD*"
},
{
"netclass": "LED",
"pattern": "*J2-Pad9*"
},
{
"netclass": "LED",
"pattern": "*J2-Pad12*"
},
{
"netclass": "Signal",
"pattern": "*CDONE*"
},
{
"netclass": "Signal",
"pattern": "*DBG*"
},
{
"netclass": "Signal",
"pattern": "*EXI_CLK*"
},
{
"netclass": "Signal",
"pattern": "*EXI_CS*"
},
{
"netclass": "Signal",
"pattern": "*EXI_INT*"
},
{
"netclass": "Signal",
"pattern": "*EXI_MISO*"
},
{
"netclass": "Signal",
"pattern": "*EXI_MOSI*"
},
{
"netclass": "Signal",
"pattern": "*EE_CLK*"
},
{
"netclass": "Signal",
"pattern": "*EE_CS*"
},
{
"netclass": "Signal",
"pattern": "*EE_DATA*"
},
{
"netclass": "Signal",
"pattern": "*EE_DO*"
},
{
"netclass": "Signal",
"pattern": "*RESET*"
},
{
"netclass": "Signal",
"pattern": "*CLK12*"
},
{
"netclass": "Signal",
"pattern": "*EXTIN*"
},
{
"netclass": "Signal",
"pattern": "*GC_ON*"
},
{
"netclass": "Signal",
"pattern": "*CC1*"
},
{
"netclass": "Signal",
"pattern": "*CC2*"
},
{
"netclass": "Signal",
"pattern": "*PR1*"
},
{
"netclass": "Signal",
"pattern": "*U8-REF*"
},
{
"netclass": "Signal",
"pattern": "*XTAL_*"
},
{
"netclass": "Signal",
"pattern": "*OSCI*"
},
{
"netclass": "Signal",
"pattern": "*OSCO*"
},
{
"netclass": "Signal",
"pattern": "*XSCO*"
},
{
"netclass": "LED",
"pattern": "*Q1-B*"
},
{
"netclass": "LED",
"pattern": "*Q2-B*"
},
{
"netclass": "ETH_DP",
"pattern": "*MDI_TX_P*"
},
{
"netclass": "ETH_DP",
"pattern": "*MDI_TX_N*"
},
{
"netclass": "ETH_DP",
"pattern": "*MDI_RX_P*"
},
{
"netclass": "ETH_DP",
"pattern": "*MDI_RX_N*"
},
{
"netclass": "PowerLV",
"pattern": "*VPHY*"
},
{
"netclass": "Power",
"pattern": "GND"
},
{
"netclass": "Power",
"pattern": "*VBST*"
},
{
"netclass": "Termination",
"pattern": "*C18-Pad1*"
},
{
"netclass": "Termination",
"pattern": "*C19-Pad1*"
},
{
"netclass": "FB_Sense",
"pattern": "*VFB*"
}
]
},
hardware/re-bba-rb/sym-lib-table
+1
View File
@@ -4,4 +4,5 @@
(lib (name "TPS562201DDCR")(type "KiCad")(uri "${KIPRJMOD}/../TPS562201DDCR.kicad_sym")(options "")(descr "TPS562201 buck (custom)"))
(lib (name "HR911105A")(type "KiCad")(uri "${KIPRJMOD}/../HR911105A.kicad_sym")(options "")(descr "HanRun HR911105A RJ45 magjack (custom)"))
(lib (name "PUSB3AB6Z_ES")(type "KiCad")(uri "${KIPRJMOD}/../PUSB3AB6Z_ES.kicad_sym")(options "")(descr "Nexperia PUSB3AB6Z 6-ch 3.3V 0.15pF TVS array (ElecSuper 2nd source)"))
(lib (name "TPS25961")(type "KiCad")(uri "${KIPRJMOD}/../TPS25961.kicad_sym")(options "")(descr "TI TPS25961 eFuse, 6-pin SON (custom)"))
)
hardware/sp1_insert/fp-lib-table
+4
View File
@@ -0,0 +1,4 @@
(fp_lib_table
(version 7)
(lib (name "hardware") (type "KiCad") (uri "${KIPRJMOD}/..") (options "") (descr "shared custom footprints (SP1_eth2sp1_reference lives here)"))
)
hardware/sp1_insert/sp1_insert.kicad_dru
+23
View File
@@ -0,0 +1,23 @@
(version 1)
# SP1 gold fingers must reach the board edge to contact the GameCube slot,
# so copper-to-edge clearance is intentionally relaxed for the connector
# footprint only. By design, not a defect. Mirrors the identical rule in
# ../re-bba-rb/re-bba-rb.kicad_dru for J3.
(rule "SP1 gold fingers - allow copper to board edge"
(condition "A.memberOfFootprint('J1') || B.memberOfFootprint('J1')")
(constraint edge_clearance (min -0.5mm)))
# JLCPCB manufacturing floor (same tier as the main board).
(rule "JLCPCB min copper clearance (0.09mm)"
(severity error)
(constraint clearance (min 0.09mm)))
(rule "JLCPCB min via/PTH drill (0.15mm)"
(severity error)
(constraint hole_size (min 0.15mm)))
(rule "JLCPCB min via pad diameter (0.25mm)"
(severity error)
(constraint via_diameter (min 0.25mm)))
(rule "JLCPCB min hole-to-hole spacing (0.2mm)"
(severity error)
(constraint hole_to_hole (min 0.2mm)))
hardware/sp1_insert/sp1_insert.kicad_pcb
+591
View File
@@ -0,0 +1,591 @@
(kicad_pcb
(version 20260206)
(generator "pcbnew")
(generator_version "10.0")
(general
(thickness 1.1412)
(legacy_teardrops no)
)
(paper "A4")
(layers
(0 "F.Cu" signal)
(4 "In1.Cu" signal)
(6 "In2.Cu" signal)
(2 "B.Cu" signal)
(9 "F.Adhes" user "F.Adhesive")
(11 "B.Adhes" user "B.Adhesive")
(13 "F.Paste" user)
(15 "B.Paste" user)
(5 "F.SilkS" user "F.Silkscreen")
(7 "B.SilkS" user "B.Silkscreen")
(1 "F.Mask" user)
(3 "B.Mask" user)
(17 "Dwgs.User" user "User.Drawings")
(19 "Cmts.User" user "User.Comments")
(21 "Eco1.User" user "User.Eco1")
(23 "Eco2.User" user "User.Eco2")
(25 "Edge.Cuts" user)
(27 "Margin" user)
(31 "F.CrtYd" user "F.Courtyard")
(29 "B.CrtYd" user "B.Courtyard")
(35 "F.Fab" user)
(33 "B.Fab" user)
(39 "User.1" user)
(41 "User.2" user)
(43 "User.3" user)
(45 "User.4" user)
)
(setup
(stackup
(layer "F.SilkS"
(type "Top Silk Screen")
)
(layer "F.Paste"
(type "Top Solder Paste")
)
(layer "F.Mask"
(type "Top Solder Mask")
(thickness 0.01)
)
(layer "F.Cu"
(type "copper")
(thickness 0.035)
)
(layer "dielectric 1"
(type "prepreg")
(thickness 0.2104)
(material "FR4")
(epsilon_r 4.5)
(loss_tangent 0.02)
)
(layer "In1.Cu"
(type "copper")
(thickness 0.0152)
)
(layer "dielectric 2"
(type "core")
(thickness 0.6)
(material "FR4")
(epsilon_r 4.5)
(loss_tangent 0.02)
)
(layer "In2.Cu"
(type "copper")
(thickness 0.0152)
)
(layer "dielectric 3"
(type "prepreg")
(thickness 0.2104)
(material "FR4")
(epsilon_r 4.5)
(loss_tangent 0.02)
)
(layer "B.Cu"
(type "copper")
(thickness 0.035)
)
(layer "B.Mask"
(type "Bottom Solder Mask")
(thickness 0.01)
)
(layer "B.Paste"
(type "Bottom Solder Paste")
)
(layer "B.SilkS"
(type "Bottom Silk Screen")
)
(copper_finish "None")
(dielectric_constraints no)
)
(pad_to_mask_clearance 0)
(allow_soldermask_bridges_in_footprints no)
(tenting
(front yes)
(back yes)
)
(covering
(front no)
(back no)
)
(plugging
(front no)
(back no)
)
(capping no)
(filling no)
(pcbplotparams
(layerselection 0x00000000_00000000_55555555_5755f5ff)
(plot_on_all_layers_selection 0x00000000_00000000_00000000_00000000)
(disableapertmacros no)
(usegerberextensions no)
(usegerberattributes yes)
(usegerberadvancedattributes yes)
(creategerberjobfile yes)
(dashed_line_dash_ratio 12)
(dashed_line_gap_ratio 3)
(svgprecision 4)
(plotframeref no)
(mode 1)
(useauxorigin no)
(pdf_front_fp_property_popups yes)
(pdf_back_fp_property_popups yes)
(pdf_metadata yes)
(pdf_single_document no)
(dxfpolygonmode yes)
(dxfimperialunits yes)
(dxfusepcbnewfont yes)
(psnegative no)
(psa4output no)
(plot_black_and_white yes)
(sketchpadsonfab no)
(plotpadnumbers no)
(hidednponfab no)
(sketchdnponfab yes)
(crossoutdnponfab yes)
(subtractmaskfromsilk no)
(outputformat 1)
(mirror no)
(drillshape 0)
(scaleselection 1)
(outputdirectory "gerbers/")
)
)
(footprint "hardware:SP1_eth2sp1_reference"
(layer "F.Cu")
(uuid "c3dff9b7-d632-448f-80ef-846fa4aaa236")
(at 100.01 98.2494)
(property "Reference" "J1"
(at 0 -11 0)
(unlocked yes)
(layer "F.SilkS")
(uuid "38fdc246-986f-4656-931c-9098d3160609")
(effects
(font
(size 1 1)
(thickness 0.15)
)
)
)
(property "Value" "SP1_INSERT"
(at 0 9.5 0)
(unlocked yes)
(layer "F.Fab")
(uuid "09d8b7a2-8e0e-4385-a411-5b5528d95069")
(effects
(font
(size 1 1)
(thickness 0.15)
)
)
)
(property "Datasheet" ""
(at 0 0 0)
(unlocked yes)
(layer "F.Fab")
(hide yes)
(uuid "baefe22d-c1f8-4f83-abc1-c0543c506a07")
(effects
(font
(size 1 1)
(thickness 0.15)
)
)
)
(property "Description" ""
(at 0 0 0)
(unlocked yes)
(layer "F.Fab")
(hide yes)
(uuid "8b8716fe-97c3-473e-b072-171d2a489c71")
(effects
(font
(size 1 1)
(thickness 0.15)
)
)
)
(attr smd)
(duplicate_pad_numbers_are_jumpers no)
(fp_line
(start -6.5 -6.4)
(end -6.5 0)
(stroke
(width 0.1)
(type solid)
)
(layer "Cmts.User")
(uuid "dfa6c775-2697-4bc0-98b5-4153a6dce288")
)
(fp_line
(start 5.9 -7)
(end -5.9 -7)
(stroke
(width 0.1)
(type solid)
)
(layer "Cmts.User")
(uuid "fa1cc527-0999-43e3-bbee-4911cef99d9d")
)
(fp_line
(start 6.5 -6.4)
(end 6.5 0)
(stroke
(width 0.1)
(type solid)
)
(layer "Cmts.User")
(uuid "a26abfe7-0d15-4f9d-86b0-59f940f6ed12")
)
(fp_arc
(start -6.5 -6.4)
(mid -6.324264 -6.824264)
(end -5.9 -7)
(stroke
(width 0.1)
(type solid)
)
(layer "Cmts.User")
(uuid "50917725-a0b9-4d21-8808-9d0fb16672aa")
)
(fp_arc
(start 5.9 -7)
(mid 6.324264 -6.824264)
(end 6.5 -6.4)
(stroke
(width 0.1)
(type solid)
)
(layer "Cmts.User")
(uuid "eba98ff8-ca8d-4f65-b41f-361504a39c10")
)
(fp_text user "${REFERENCE}"
(at 0 2.5 0)
(unlocked yes)
(layer "F.Fab")
(uuid "5cedd119-6420-42e7-a09a-2282fd0981a7")
(effects
(font
(size 1 1)
(thickness 0.15)
)
)
)
(pad "1" smd rect
(at -5.5 0.4206 180)
(size 1.5 13.6412)
(layers "B.Cu" "B.Mask")
(pinfunction "EXTIN")
(pintype "input+no_connect")
(uuid "8160b939-ce92-4631-9852-2a26e1aea0cc")
)
(pad "2" smd rect
(at -4.5 0.4206 180)
(size 1.5 13.6412)
(layers "F.Cu" "F.Mask")
(net "EXI_GND")
(pinfunction "GNDs")
(pintype "input")
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hardware/sp1_insert/sp1_insert.kicad_prl
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1,
2
],
[
0,
1,
0,
0,
0,
0,
1,
1,
2,
1,
1,
2
],
[
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
2
],
[
1,
1,
1,
1,
1,
0,
1,
1,
1,
1,
1,
2
],
[
0,
0,
0,
1,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
1,
2,
0,
0,
1,
0,
2,
2,
2,
2
],
[
0,
2,
0,
1,
0,
0,
1,
0,
2,
0,
0,
2
],
[
0,
2,
1,
1,
0,
0,
1,
0,
2,
0,
0,
2
],
[
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2
]
],
"rule_severities": {
"bus_definition_conflict": "error",
"bus_entry_needed": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"endpoint_off_grid": "warning",
"extra_units": "error",
"field_name_whitespace": "warning",
"footprint_filter": "ignore",
"footprint_link_issues": "warning",
"four_way_junction": "ignore",
"ground_pin_not_ground": "warning",
"hier_label_mismatch": "error",
"isolated_pin_label": "warning",
"label_dangling": "error",
"label_multiple_wires": "warning",
"lib_symbol_issues": "warning",
"lib_symbol_mismatch": "warning",
"missing_bidi_pin": "warning",
"missing_input_pin": "warning",
"missing_power_pin": "error",
"missing_unit": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"same_local_global_label": "warning",
"similar_label_and_power": "warning",
"similar_labels": "warning",
"similar_power": "warning",
"simulation_model_issue": "ignore",
"single_global_label": "ignore",
"stacked_pin_name": "warning",
"unannotated": "error",
"unconnected_wire_endpoint": "warning",
"undefined_netclass": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
"wire_dangling": "error"
}
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "sp1_insert.kicad_pro",
"version": 3
},
"net_settings": {
"classes": [
{
"bus_width": 12,
"clearance": 0.15,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 2147483647,
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.2,
"tuning_profile": "",
"via_diameter": 0.6,
"via_drill": 0.3,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.15,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "EXI_GND",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 1,
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.3,
"tuning_profile": "",
"via_diameter": 0.6,
"via_drill": 0.3,
"wire_width": 6
}
],
"meta": {
"version": 5
},
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": [
{
"netclass": "EXI_GND",
"pattern": "EXI_GND"
}
]
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"plot": "gerbers/",
"specctra_dsn": "",
"step": "",
"svg": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"annotate_start_num": 0,
"annotation": {
"method": 0,
"sort_order": 0
},
"bom_export_filename": "${PROJECTNAME}.csv",
"bom_fmt_presets": [],
"bom_fmt_settings": {
"field_delimiter": ",",
"keep_line_breaks": false,
"keep_tabs": false,
"name": "CSV",
"ref_delimiter": ",",
"ref_range_delimiter": "",
"string_delimiter": "\""
},
"bom_presets": [],
"bom_settings": {
"exclude_dnp": false,
"fields_ordered": [
{
"group_by": false,
"label": "Reference",
"name": "Reference",
"show": true
},
{
"group_by": false,
"label": "Qty",
"name": "${QUANTITY}",
"show": true
},
{
"group_by": true,
"label": "Value",
"name": "Value",
"show": true
},
{
"group_by": true,
"label": "DNP",
"name": "${DNP}",
"show": true
},
{
"group_by": true,
"label": "Exclude from BOM",
"name": "${EXCLUDE_FROM_BOM}",
"show": true
},
{
"group_by": true,
"label": "Exclude from Board",
"name": "${EXCLUDE_FROM_BOARD}",
"show": true
},
{
"group_by": true,
"label": "Footprint",
"name": "Footprint",
"show": true
},
{
"group_by": false,
"label": "Datasheet",
"name": "Datasheet",
"show": true
},
{
"group_by": false,
"label": "Check_prices",
"name": "Check_prices",
"show": false
},
{
"group_by": false,
"label": "Manufacturer",
"name": "Manufacturer",
"show": false
},
{
"group_by": false,
"label": "MF",
"name": "MF",
"show": false
},
{
"group_by": false,
"label": "MP",
"name": "MP",
"show": false
},
{
"group_by": false,
"label": "Package",
"name": "Package",
"show": false
},
{
"group_by": false,
"label": "Price",
"name": "Price",
"show": false
},
{
"group_by": false,
"label": "Purchase-URL",
"name": "Purchase-URL",
"show": false
},
{
"group_by": false,
"label": "SnapEDA_Link",
"name": "SnapEDA_Link",
"show": false
},
{
"group_by": false,
"label": "Availability",
"name": "Availability",
"show": false
},
{
"group_by": false,
"label": "Description",
"name": "Description",
"show": false
},
{
"group_by": false,
"label": "#",
"name": "${ITEM_NUMBER}",
"show": false
},
{
"group_by": false,
"label": "ESR",
"name": "ESR",
"show": false
},
{
"group_by": false,
"label": "PARTREV",
"name": "PARTREV",
"show": false
},
{
"group_by": false,
"label": "LCSC",
"name": "LCSC",
"show": false
},
{
"group_by": false,
"label": "MAXIMUM_PACKAGE_HEIGHT",
"name": "MAXIMUM_PACKAGE_HEIGHT",
"show": false
},
{
"group_by": false,
"label": "STANDARD",
"name": "STANDARD",
"show": false
},
{
"group_by": false,
"label": "Tolerance",
"name": "Tolerance",
"show": false
},
{
"group_by": false,
"label": "Type",
"name": "Type",
"show": false
},
{
"group_by": false,
"label": "V",
"name": "V",
"show": false
},
{
"group_by": false,
"label": "CL",
"name": "CL",
"show": false
},
{
"group_by": false,
"label": "Current",
"name": "Current",
"show": false
},
{
"group_by": false,
"label": "MPN",
"name": "MPN",
"show": false
},
{
"group_by": false,
"label": "C0",
"name": "C0",
"show": false
}
],
"filter_string": "",
"group_symbols": true,
"include_excluded_from_bom": true,
"name": "",
"sort_asc": true,
"sort_field": "Reference"
},
"bus_aliases": {},
"connection_grid_size": 50.0,
"drawing": {
"dashed_lines_dash_length_ratio": 12.0,
"dashed_lines_gap_length_ratio": 3.0,
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"field_names": [],
"hop_over_size_choice": 0,
"intersheets_ref_own_page": false,
"intersheets_ref_prefix": "",
"intersheets_ref_short": false,
"intersheets_ref_show": false,
"intersheets_ref_suffix": "",
"junction_size_choice": 3,
"label_size_ratio": 0.375,
"operating_point_overlay_i_precision": 3,
"operating_point_overlay_i_range": "~A",
"operating_point_overlay_v_precision": 3,
"operating_point_overlay_v_range": "~V",
"overbar_offset_ratio": 1.23,
"pin_symbol_size": 25.0,
"text_offset_ratio": 0.15
},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"meta": {
"version": 1
},
"page_layout_descr_file": "",
"plot_directory": "",
"reuse_designators": true,
"subpart_first_id": 65,
"subpart_id_separator": 0,
"top_level_sheets": [
{
"filename": "re-bba-rb.kicad_sch",
"name": "ReBBaRb",
"uuid": "dbb182a6-d579-468e-b98b-6f0950da9e3a"
}
],
"used_designators": "",
"variants": []
},
"sheets": [],
"text_variables": {},
"tuning_profiles": {
"meta": {
"version": 0
},
"tuning_profiles_impedance_geometric": []
}
}
hardware/sp1_insert/sym-lib-table
+4
View File
@@ -0,0 +1,4 @@
(sym_lib_table
(version 7)
(lib (name "GameCube")(type "KiCad")(uri "${KIPRJMOD}/../sp1_test_plug/symbols/GameCube.kicad_sym")(options "")(descr "GameCube SP1 connector"))
)