Add W5100S MDI termination network to ethernet schematic

Per the WIZnet W5100S reference schematic (note 4: "to avoid the 100M
overshoot, place the 49.9 resistors and 0.1uF capacitor near the MDI
pin"): R26/R27 (49.9R 1%) from TXOP/TXON to a common node bypassed by
C18 (100nF) to GND, and R28/R29 + C19 likewise for RXIP/RXIN. Attached
on the PHY-side nets (chip side of D4/D5). BOM fields populated
(UNI-ROYAL 0402WGF4999TCE / LCSC C25120, Samsung CL05B104KO5NNNC /
C1525). Optional 3.3R series dampers deliberately omitted.

Schematic only - the 6 footprints still need placing/routing next to
U11 pins 2/3/5/6 (Update PCB from Schematic). DRC parity reports
exactly those 6 missing footprints and nothing else.

Verified: ERC 0, netlist 107->113 components, termination nets match
the reference topology.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>

hardware/re-bba-rb/TODO.md

@@ -25,12 +25,19 @@ W5100S reference schematic, and JLCPCB manufacturing limits. ERC/DRC: clean.
       - [ ] Use this final pin map when writing the board PCF (see Broader
             items): MOSI = pin 4, MISO = pin 3, CLK = 44 (G6), CS = 45,
             INT = 46.
-- [ ] **W5100S MDI termination network missing** (`ethernet.kicad_sch`).
+- [ ] **W5100S MDI termination network** (`ethernet.kicad_sch`) — schematic
-      Per WIZnet W5100S reference schematic: 49.9 Ω from each of
+      part DONE 2026-07-17: added R26/R27 (49.9 Ω 1%, LCSC C25120) from
-      TXOP/TXON/RXIP/RXIN to a common node with 0.1 µF to GND, placed near the
+      TXOP/TXON to a common node + C18 (100 nF) to GND, and R28/R29 + C19 for
-      chip ("to avoid the 100M overshoot"); optionally 3.3 Ω series damping in
+      RXIP/RXIN, on the PHY-side nets per the WIZnet reference schematic.
-      each line. Board routes the pairs straight through D4/D5 to the magjack.
+      ERC 0; netlist verified. Remaining (PCB rework):
-      - [ ] Add 4× 49.9 Ω 1% + 2× 0.1 µF termination.
+      - [ ] Place the 6 new footprints (Update PCB from Schematic / F8 pulls
+            them in) **next to U11 pins 2/3/5/6** — WIZnet: "place the 49.9
+            resistors and 0.1uF capacitor near the MDI pin of W5100S".
+      - [ ] Keep the pair stubs to the resistors short; the ETH_DP netclass
+            width/gap rules still apply to the through-line.
+      - [ ] Optional (left out deliberately): 3.3 Ω series damping resistors
+            in each line (WIZnet note 6, EMI reduction) — would require
+            breaking the pairs; add only if EMI testing demands.
       - [ ] Place C51/C52 physically at J2 pins 4/5 (center taps).
       - [ ] Reconsider D4/D5 (USBLC6 on the line side of the magnetics):
             unusual — transformer already isolates; their VBUS pins float so