docs: correct stale 'part fields blank' notes + flag kicad-cli zone-refill DRC trap

All eFuse/RExt/EE-CS parts (U13, R43-R47, C66, R44, D13) are picked with
MPN+LCSC in the live BOM and placed+routed on the PCB - the TODO/REVIEW
notes calling their fields 'intentionally blank' were written when the
parts were first added and never updated. Corrected to reflect the
committed state.

Also documents the kicad-cli DRC gotcha that caused a false alarm: it
does not refill zones, so it reports phantom GND-via-in-3V3-pour and
thermal-pad clearance errors (actual 0.000mm) on a board the GUI reports
clean. Added a warning at the top of TODO and in REVIEW section 7 so no
future session mistakes it for a real defect.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>

hardware/re-bba-rb/REVIEW.md

@@ -195,9 +195,10 @@ datasheet extraction, WebSearch/WebFetch for parts and reference designs.
   (F=25 MHz, ESR=50 Ω per the 16–31 MHz band, C0=3 pF max, CL=12 pF,
   gm=16.7 mA/V): **margin 7.53×**, against a DS requirement of ≥5 (the
   "6.99 dB" in Table 8 is 10·log₁₀5). **Ceiling is 100 Ω** — 120 Ω already
-  fails the startup spec. Fitted value is a starting point; part fields are
-  intentionally blank so it is re-selected/confirmed at bring-up by
-  measuring drive level.
+  fails the startup spec. Part is PICKED (UNI-ROYAL 0402WGF4999TCE, C25120 —
+  the same 49.9 Ω already on R26–R29); the 49.9 Ω value is still a starting
+  point to **confirm at bring-up** by measuring drive level (bench action
+  only — the BOM line is not blank).
 - **Crystal symbol properties corrected 2026-07-31** (they were metadata-only
   errors, no copper impact, but they caused the regression above):
   Y1 CL 18 pF→**12 pF**, ESR 50 Ω→**80 Ω** (DS band 12–15 MHz),
@@ -342,10 +343,19 @@ datasheet extraction, WebSearch/WebFetch for parts and reference designs.
 
 ## 7. PCB global / JLCPCB — REVIEWED, PASS
 
-- **DRC**: 0 errors / 0 unconnected / 0 parity as of each review point
-  (remaining parity items = the 11 debug/fix footprints awaiting placement +
-  3 FTDI reroutes + R3 value sync — all listed by F8). Warnings are
-  silkscreen cosmetics only (~150; JLC auto-clips).
+- ⚠️ **`kicad-cli pcb drc` DOES NOT REFILL ZONES — do not panic at its output.**
+  It evaluates the zone-fill state *as saved in the file*, so any GND stitching
+  via sitting in the 3V3 pour, or a thermal pad in the GND pour, is reported as
+  a phantom `clearance`/`hole_clearance` error with "actual 0.0000 mm" — because
+  the saved fill still has copper where the GUI would carve a void. **The KiCad
+  GUI refills all zones before DRC**, so the GUI (the authority) shows these
+  clean. Confirmed 2026-08-02: a command-line DRC reported 18 such
+  "errors" (14 GND-vias-over-3V3, 4 on U13's thermal pad) on a board the GUI
+  reports clean. If you must DRC from the CLI, open the board in the GUI, run
+  "Fill All Zones" (B), save, THEN run `kicad-cli` — or just trust the GUI.
+  The board is DRC-CLEAN in KiCad.
+- **DRC (GUI, authoritative)**: 0 errors / 0 unconnected / 0 parity. Warnings
+  are silkscreen cosmetics only (~150–170; JLC auto-clips).
 - **JLC capability floor**: encoded as error-severity rules in
   `re-bba-rb.kicad_dru` (0.09 mm trace/space, 0.15 mm drill, 0.2 mm
   hole-to-copper etc.) — passing. Diff-pair impedance rules (USB 90 Ω,