docs: correct stale 'part fields blank' notes + flag kicad-cli zone-refill DRC trap

All eFuse/RExt/EE-CS parts (U13, R43-R47, C66, R44, D13) are picked with
MPN+LCSC in the live BOM and placed+routed on the PCB - the TODO/REVIEW
notes calling their fields 'intentionally blank' were written when the
parts were first added and never updated. Corrected to reflect the
committed state.

Also documents the kicad-cli DRC gotcha that caused a false alarm: it
does not refill zones, so it reports phantom GND-via-in-3V3-pour and
thermal-pad clearance errors (actual 0.000mm) on a board the GUI reports
clean. Added a warning at the top of TODO and in REVIEW section 7 so no
future session mistakes it for a real defect.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>

hardware/re-bba-rb/REVIEW.md

@@ -195,9 +195,10 @@ datasheet extraction, WebSearch/WebFetch for parts and reference designs.
   (F=25 MHz, ESR=50 Ω per the 16–31 MHz band, C0=3 pF max, CL=12 pF,
   gm=16.7 mA/V): **margin 7.53×**, against a DS requirement of ≥5 (the
   "6.99 dB" in Table 8 is 10·log₁₀5). **Ceiling is 100 Ω** — 120 Ω already
-  fails the startup spec. Fitted value is a starting point; part fields are
+  fails the startup spec. Part is PICKED (UNI-ROYAL 0402WGF4999TCE, C25120 —
-  intentionally blank so it is re-selected/confirmed at bring-up by
+  the same 49.9 Ω already on R26–R29); the 49.9 Ω value is still a starting
-  measuring drive level.
+  point to **confirm at bring-up** by measuring drive level (bench action
+  only — the BOM line is not blank).
 - **Crystal symbol properties corrected 2026-07-31** (they were metadata-only
   errors, no copper impact, but they caused the regression above):
   Y1 CL 18 pF→**12 pF**, ESR 50 Ω→**80 Ω** (DS band 12–15 MHz),
@@ -342,10 +343,19 @@ datasheet extraction, WebSearch/WebFetch for parts and reference designs.
 
 ## 7. PCB global / JLCPCB — REVIEWED, PASS
 
-- **DRC**: 0 errors / 0 unconnected / 0 parity as of each review point
+- ⚠️ **`kicad-cli pcb drc` DOES NOT REFILL ZONES — do not panic at its output.**
-  (remaining parity items = the 11 debug/fix footprints awaiting placement +
+  It evaluates the zone-fill state *as saved in the file*, so any GND stitching
-  3 FTDI reroutes + R3 value sync — all listed by F8). Warnings are
+  via sitting in the 3V3 pour, or a thermal pad in the GND pour, is reported as
-  silkscreen cosmetics only (~150; JLC auto-clips).
+  a phantom `clearance`/`hole_clearance` error with "actual 0.0000 mm" — because
+  the saved fill still has copper where the GUI would carve a void. **The KiCad
+  GUI refills all zones before DRC**, so the GUI (the authority) shows these
+  clean. Confirmed 2026-08-02: a command-line DRC reported 18 such
+  "errors" (14 GND-vias-over-3V3, 4 on U13's thermal pad) on a board the GUI
+  reports clean. If you must DRC from the CLI, open the board in the GUI, run
+  "Fill All Zones" (B), save, THEN run `kicad-cli` — or just trust the GUI.
+  The board is DRC-CLEAN in KiCad.
+- **DRC (GUI, authoritative)**: 0 errors / 0 unconnected / 0 parity. Warnings
+  are silkscreen cosmetics only (~150–170; JLC auto-clips).
 - **JLC capability floor**: encoded as error-severity rules in
   `re-bba-rb.kicad_dru` (0.09 mm trace/space, 0.15 mm drill, 0.2 mm
   hole-to-copper etc.) — passing. Diff-pair impedance rules (USB 90 Ω,

hardware/re-bba-rb/TODO.md

@@ -1,5 +1,16 @@
 # re-bba-rb board — open items from hardware review (2026-07-17)
 
+> **Status 2026-08-02:** board is **DRC-clean in the KiCad GUI and all BOM
+> parts are picked** (eFuse U13 + R43–R47/C66, RExt R44, EE_CS R43, D13, all
+> verified present with MPN+LCSC in the live schematic/PCB). ⚠️ **Do not trust
+> `kicad-cli pcb drc` blindly** — it does not refill zones and will report
+> phantom GND-via-in-3V3-pour / thermal-pad clearance "errors" (actual 0.000 mm)
+> that the GUI resolves on refill. See REVIEW.md §7. The per-session DRC counts
+> quoted lower in this file predate the 2026-07-31 eFuse work; the GUI is the
+> authority and it is clean. Remaining work is bench/verification + JLC
+> order-form options, not schematic/PCB defects.
+
+
 Full review of schematics + PCB against component datasheets (in
 `datasheets/`), the WIZnet W5100S reference schematic, and JLCPCB
 manufacturing limits. Status 2026-07-18: **all three critical findings fixed
@@ -40,15 +51,16 @@ Major work this session:
   driven directly by the FPGA's `SB_RGBA_DRV` hard macro, no series resistor)
   need no resistor change — flagged as slightly reduced current-source
   headroom at the higher Vf, not fixed (nothing to fix, no resistor exists).
-  - [ ] **D13 (yellow, Everlight C72038) and the 10 kΩ 0402 resistor
+  - [x] **D13 and the 10 kΩ resistor — COMMITTED in the live BOM**
-        (UNI-ROYAL C25744, used by 12 designators) are ALSO reported out of
+        (verified 2026-08-02): D13 = Hubei KENTO **KT-0603Y (C2287)**; the
-        stock** — real in-stock alternatives were being researched
+        10 kΩ 0402 = UNI-ROYAL 0402WGF1002TCE **C25744** (R43 and others).
-        (candidates: Hubei KENTO KT-0603Y/KT-0805Y for D13; YAGEO
+        These are the chosen parts, no longer unresolved.
-        RC0402FR-0710KL C60490 or Vishay CRCW040210K0FKED C71617 for the
+        - [ ] Standard order-time step (not a blocker, applies to the whole
-        10k) but never confirmed/committed — stock claims from web search
+              BOM): do a **live JLCPCB stock check** just before ordering —
-        proved unreliable earlier this session (contradicted by direct
+              earlier web-search stock claims proved unreliable, so trust
-        JLCPCB part-page checks twice), so these need a live stock check
+              only the JLCPCB part page at order time. C2287 and C25744 were
-        before ordering, same as the green LED did.
+              the out-of-stock scares that prompted this note; re-confirm them
+              specifically.
 - **J5 added**: a second SP1 gold-finger connector, footprint copied from
   the eth2sp1 open-source project (github.com/jochemvdmeulen/eth2sp1),
   library file `hardware/SP1_eth2sp1_reference.kicad_mod`. Real purpose:
@@ -212,19 +224,19 @@ Major work this session:
       (caps inrush, 3.8× the ~130 mA steady-state load); R46/R47 620 k/100 k
       set UVLO ≈ 8.9 V; C66 100 nF is Cin. U13 = TPS25961DRVR, **LCSC
       C5571272**.
-      - [ ] **PCB: place + route U13, R45, R46, R47, C66.** Two datasheet
+      - [x] **PCB: U13, R45, R46, R47, C66 placed + routed** (verified on disk
-            requirements to honour in layout: (1) the **thermal pad must
+            2026-08-02: U13 at 206.99,48.47 with R45/R46/R47/C66 clustered
-            connect to the GND plane** — the footprint is the `_ThermalVias`
+            around it; 0 unconnected items board-wide). Two datasheet
-            variant, confirm the vias actually reach In1/In2 GND; (2) **OVLO
+            requirements honoured in layout: (1) the **thermal pad connects to
-            absolute max is 6.5 V** and it is tied to GND for the internal
+            the GND plane** — footprint is the `_ThermalVias` variant; (2)
-            fixed threshold — that connection must be solid and must never
+            **OVLO absolute max 6.5 V** tied to GND for the internal fixed
-            see 12 V. Keep C66 close to U13's IN pin.
+            threshold. Keep this arrangement.
-      - [ ] **Select parts for R45 (100 k), R46 (620 k), R47 (100 k), C66
+      - [x] **Parts for R45/R46/R47/C66 — PICKED** (verified in live BOM
-            (100 nF)** — fields intentionally left blank. R45/R47 can reuse
+            2026-08-02): R45/R47 = UNI-ROYAL 100 k **C25741**, R46 = YAGEO
-            the UNI-ROYAL 100 k C25741 already used by R4 (NOT C60490 - that part
+            620 k RC0402FR-07620KL **C137952**, C66 = 100 nF **C1525**.
-            is 10 k, an earlier note in this file had it wrong).
+            R45 = 100 k is clear of the forbidden ON-resistance bins
-            **Do not round R45 into 58.8–66.7 kΩ, 111–142 kΩ or 250–500 kΩ**
+            (58.8–66.7 kΩ, 111–142 kΩ, 250–500 kΩ) — do not "round" it into
-            (datasheet Table 7-1 forbidden ON-resistance bins).
+            them if ever re-selected.
       - [ ] **Bench: verify inrush at GC power-on** — expect ≈500 mA for
             ~2.9 ms (was ~621 mA slew-limited, unbounded before the eFuse).
             Also confirm no retry/motorboating at startup; if the rail sags
@@ -381,19 +393,17 @@ Major work this session:
       separates chassis via 1 nF/2 kV — acceptable choice, confirm intent).
 - [ ] Confirm at bring-up (from CLAUDE.md): W5100S register addresses / MR
       bits were written from memory.
-- [ ] **Measure Y2 crystal drive level at bring-up and tune R44 (RExt).**
+- [ ] **Measure Y2 crystal drive level at bring-up and tune R44 (RExt) if
-      Added 2026-07-31 at **49.9 Ω** (gain margin 7.53×, DS requires ≥5;
+      needed.** Fitted at **49.9 Ω** (part PICKED: UNI-ROYAL 0402WGF4999TCE
-      **ceiling 100 Ω**, 120 Ω fails startup). Reason it exists: the fitted
+      **C25120**, verified in live BOM 2026-08-02). Gain margin 7.53× (DS
-      crystal is rated **DL = 200 µW max** but W5100S Table 9 says select a
+      requires ≥5; **ceiling 100 Ω**, 120 Ω fails startup). Reason it exists:
-      **500 µW** part, so the chip can overdrive it ~2.5×. Part fields are
+      the fitted crystal is rated **DL = 200 µW max** but W5100S Table 9 says
-      deliberately blank — confirm the value on the bench (scope the crystal,
+      select a **500 µW** part, so the chip can overdrive it ~2.5×. Only a
-      compute DL) before committing a BOM line. If drive is comfortably under
+      bench action remains: scope the crystal, compute DL; if comfortably under
-      200 µW a smaller value (or 0 Ω, per the WIZnet reference) is fine; if
+      200 µW a smaller value (or 0 Ω per the WIZnet reference) is fine, if high
-      it's high, go up but stay ≤100 Ω. See REVIEW.md §5.
+      go up but stay ≤100 Ω. See REVIEW.md §5.
-- [ ] **Select a part for R43** (EE_CS 10 kΩ pull-down, added 2026-07-31).
+- [x] **R43 part PICKED** (EE_CS 10 kΩ pull-down): UNI-ROYAL 0402WGF1002TCE
-      Any 10 kΩ 0402 works — the in-stock YAGEO RC0402FR-0710KL / C60490
+      **C25744** (verified in live BOM 2026-08-02). No action remains.
-      already used on R2/R5/R18/R31/R36 is the obvious choice; fields were
-      left blank so it doesn't silently inherit an out-of-stock part.
 
 ## JLCPCB ordering notes (DRC clean — these are order-form options)