Support BOTH command-space forms: Swiss's 4-byte and libogc's 2-byte
Reading Swiss's own driver (cube/patches/bba/bba.c) shows the previous commit
fixed libogc and BROKE Swiss. The two disagree, and both are real:
Swiss bba_cmd_out8: exi_imm_read_write(0x40<<24 | reg<<24 | val, 4)
-> ONE 4-byte transfer [0x40|reg, 00, 00, val], and bba_cmd_in8
returns the LOW byte, so a read response must be in BYTE 3.
libogc2 bba_cmd_outsnosel: req = (reg<<8)|0x4000;
EXI_ImmEx(&req, 2, WRITE); EXI_ImmEx(val, len, WRITE)
-> THREE bytes, value in byte 2, and a read takes byte 2.
stock libogc: identical to libogc2 (read out of libbba.a).
They share bytes 0 and 1 and differ only in how many bytes follow, so one
decoder serves both: take the LAST data byte before CS rise as the write value
(Swiss sends [00, val], libogc sends [val] -- last is val either way), and push
a read response TWICE so bytes 2 and 3 both carry it. Swiss clocks 4 bytes and
pops both; libogc clocks 3 and leaves one, which the next transaction's header
pops drain -- a 2-byte header gives exactly one drain slot, so the leftover is
bounded at one and cannot accumulate.
Critically this means NO auto-increment of cmd_reg across the data phase: that
applied Swiss's padding 00 to the register and val to reg+1, which is precisely
how the libogc-only version broke Swiss.
T12 covers the Swiss form and asserts bytes 2 AND 3; T10 keeps the libogc form.
Both mutation-tested: re-adding the auto-increment fails T12 with 0x00 in both
slots, and pushing the response once fails T12's byte 3. gc_bba_test gains
"cmd-space Swiss" alongside "cmd-space write", with bba_cmd_write4/read4.
Also corrects two things in CLAUDE.md now checkable against three drivers:
- NO driver writes TWD -- not Swiss, not libogc, not libogc2. The "GC sets
TWD before streaming" note was self-confirming: t_tx writes TWD because we
wrote t_tx. The counted TXDATA length is the primary path, not a fallback.
- Swiss's exi_dma_write rounds the length UP to 32 bytes (OSRoundUp32B), so
TXDATA gets up to 31 trailing bytes past the frame and a counted length sends
that much extra. Real hardware must do the same since Swiss works on it;
trailing padding past the IP total length is ignored. A 1514-byte frame
rounds to 1536 though, over the 1518 maximum.
Both drivers trigger TX with NCRA ST1, which the existing any-ST test accepts.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
This commit is contained in:
@@ -1065,25 +1065,51 @@ REGISTER space (16-bit reg) 4-byte header, then a SEPARATE data phase
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write: [0xC0, reg>>8, reg&0xFF, 0x00] then N bytes written
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```
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⚠️ **Command space is a 2-byte header + data phase — corrected 2026-10-10.**
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This file previously said "one 4-byte READWRITE transfer,
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`[0x40|reg, 00, 00, data]`", and the decoder followed it: it waited for a
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fourth byte, consumed the DATA byte as header byte 2, and **silently dropped
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every command-space write.** libogc's `__bba_init` writes command register 2
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(its interrupt mask) at both the start and the end of init, so none of that
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would have taken effect. The real shape, from the disassembly:
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⚠️ **COMMAND SPACE HAS TWO FORMS AND BOTH ARE REAL — settled 2026-10-10 by
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reading all three drivers.** Register space is the same everywhere; command
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space is not:
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```
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EXI_Imm (len=2, write) -> 42 00 the WHOLE header
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EXI_Sync
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EXI_ImmEx(len=1, write) -> 00 the data
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```
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| contract | Swiss patch | libogc (stock) | libogc2 |
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|---|---|---|---|
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| RX descriptor | packed LE bitfield | packed LE bitfield | packed LE bitfield |
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| register space | 4-byte header + data phase | same | same |
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| **command space** | **ONE 4-byte transfer**, value/response in **byte 3** | 2-byte header + data phase, **byte 2** | 2-byte header + data phase, **byte 2** |
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| TWD on TX | **never written** | never written | never written |
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| TX trigger | NCRA **ST1** | NCRA ST1 (`0x04`) | NCRA ST1 |
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Three bytes between CS fall and CS rise, not four. `0x4200 = 0x4000 |
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(reg << 8)`. The device-ID read survived the wrong decode only because
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`SPIMode3Slave` answers it on a fast path independent of the FSM — which is
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exactly why no test caught it. `bba_register_file` **T10** now writes command
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register 2 and reads it back, and is mutation-tested against the 4-byte decode.
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Sources, so this can be re-checked rather than re-guessed:
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- Swiss — `cube/patches/bba/bba.c`, `bba_cmd_out8`:
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`exi_imm_read_write(0x40<<24 | (reg&0x3F)<<24 | val, 4)`, and `bba_cmd_in8`
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returns the **low byte** of that 32-bit result.
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- libogc2 — `lwip/arch/gc/netif/gcif.c`, `bba_cmd_outsnosel`:
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`req = (reg<<8)|0x4000; EXI_ImmEx(&req, 2, WRITE); EXI_ImmEx(val, len, WRITE)`.
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- stock libogc — the same, read out of `libbba.a` (`gcif.o`, `__bba_init`):
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`EXI_Imm(len=2)` of `42 00`, then `EXI_ImmEx(len=1)` of the data.
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**How one decoder serves both:** they share bytes 0 and 1, and differ only in
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how many bytes follow. So the device takes the **LAST data byte before CS
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rise** as the write value (Swiss sends `[00, val]`, libogc sends `[val]` —
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last is `val` either way), and **pushes a read response TWICE** so byte 2 and
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byte 3 both carry it. Swiss clocks 4 bytes and pops both copies; libogc clocks
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3 and leaves one, which the next transaction's header pops drain — a 2-byte
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header gives exactly one drain slot, so the leftover is bounded at one and
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cannot accumulate.
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⚠️ **There must be NO auto-increment of `cmd_reg` across the data phase.** It
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would apply Swiss's padding `0x00` to the register and `val` to `reg+1`. This
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is how the libogc-only version broke Swiss.
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History worth keeping, because the failure mode repeated: this file first had
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Swiss's 4-byte form only, so libogc's writes were dropped (the decoder waited
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for a fourth byte and ate the data byte as header byte 2). It was then
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"fixed" to libogc's form only, which would have dropped Swiss's writes. Only
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reading all three drivers showed that neither is "the" driver. The device-ID
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read masked the original bug throughout, because `SPIMode3Slave` answers it on
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a fast path independent of this FSM.
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Tests: `bba_register_file` **T10** (libogc form) and **T12** (Swiss form,
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asserting bytes 2 AND 3), both mutation-tested — re-adding the auto-increment
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fails T12, and pushing the response once fails T12's byte 3.
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NCRA, IR, NWAYS, RWP, RRP, PAR… all live in the REGISTER space
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(`bba_in8`/`bba_out8`/`bba_ins`/`bba_outs`). Only the device-ID query uses a
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short header — the single case where the two formats coincide.
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@@ -1250,8 +1276,13 @@ parallel master is the default — see "W5100 vs W5500".)
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| 2 | read reg `0x0000` (NCRA) |
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| 3 | write reg `0x0000` = `0x04` (NCRA ST) |
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⚠️ **There is no `TWD_LO`/`TWD_HI` write anywhere**, so the device has to
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COUNT the bytes it was handed. `BBARegisterFile` now keeps `txdata_cnt`,
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⚠️ **No driver writes `TWD_LO`/`TWD_HI` — not Swiss, not libogc, not
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libogc2** (Swiss: `bba_output` is `bba_outs(BBA_WRTXFIFOD, data, size)` then
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NCRA ST1; libogc2: `bba_outsregister(BBA_WRTXFIFOD)` then NCRA ST1). So the
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device has to COUNT the bytes it was handed. The TWD path is OUR test app's
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convention, not a driver's — which is why the "GC sets TWD before streaming"
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note in the TWD fix was self-confirming: `t_tx` writes TWD because we wrote
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`t_tx`. `BBARegisterFile` now keeps `txdata_cnt`,
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incremented per byte accepted at `0x0048`, and the NCRA ST fallback queues
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**that** rather than `tx_frame_len`. Previously it queued `tx_frame_len`,
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which a driver that skips TWD never sets — so the frame would have gone out
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@@ -1265,6 +1296,14 @@ before streaming is what lets `TXFrameDrain` consume concurrently and keeps
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`tx_bytes` a rate-matching buffer instead of whole-frame storage (see the TWD
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fix note). Swiss writes TWD; libogc does not. Support both.
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⚠️ **Swiss rounds the DMA length UP to 32 bytes** (`exi_dma_write` sets
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`EXI[..][2] = OSRoundUp32B(len)`), so TXDATA receives up to 31 trailing bytes
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beyond the frame. With a counted length the frame goes out that much longer.
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Real hardware must behave the same way, since Swiss works on it — trailing
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padding past the IP total length is ignored by receivers. Worth knowing before
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treating a slightly-too-long TX frame as a bug. Note a 1514-byte frame rounds
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to 1536, over the 1518 maximum.
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⚠️ **libogc streams the payload with `EXI_Dma`** — the 32-byte-aligned bulk via
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`EXI_Dma` after a `PPCDCacheStoreAsync`, then `EXI_ImmEx` for the remainder.
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This file says elsewhere that EXI DMA *writes* are avoided because the GC's
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+102
-30
@@ -257,6 +257,8 @@ class BBARegisterFile(Elaboratable):
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cmd_space = Signal() # this transaction is a command access
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cmd_reg = Signal(6)
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cmd_wreg = Signal(6) # target of a pending command-space write
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cmd_have = Signal() # at least one data byte seen this txn
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cmd_pushes = Signal(2) # command-read responses pushed
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byte_ctr = Signal(3) # response-byte index (device-ID sequence)
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cmd_wr = Signal() # command-space write pending
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prefetched = Signal() # first response byte already pushed
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@@ -378,7 +380,8 @@ class BBARegisterFile(Elaboratable):
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# PREVIOUS transaction would be pushed as this
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# one's first response and shift the whole
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# read by one.
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sp_pending.eq(0)]
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sp_pending.eq(0),
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cmd_have.eq(0), cmd_pushes.eq(0)]
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with m.If(self.rx_data[7]): # register space
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m.d.sync += cmd_space.eq(0)
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m.next = "RHDR_HI"
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@@ -448,25 +451,39 @@ class BBARegisterFile(Elaboratable):
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m.d.comb += [self.tx_data.eq(rd_val), self.tx_en.eq(1)]
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m.d.sync += [eff_addr.eq(eff_addr + 1), prefetched.eq(1)]
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# ── command space: a 2-BYTE header, then a data phase ─────────
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# ── command space: 2-byte header, then a data phase ───────────
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#
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# [0x40|reg, 0x00] + N data bytes written, or
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# [reg, 0x00] + N data bytes read.
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# ⚠️ THE TWO REAL DRIVERS DISAGREE ON THE LENGTH, and both must
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# work. Checked against the source, not guessed:
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#
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# ⚠️ NOT a single 4-byte transfer. This file used to decode
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# [reg, 00, 00, data] and wait for a fourth byte, taking the DATA
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# byte as header byte 2 -- so every command-space WRITE was
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# silently dropped. libogc's own driver (see the init map in
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# CLAUDE.md) does, for a write of 0x00 to command register 2:
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# Swiss (cube/patches/bba/bba.c, bba_cmd_out8 / bba_cmd_in8):
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# exi_imm_read_write(0x40<<24 | reg<<24 | val, 4)
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# -> ONE 4-byte transfer [0x40|reg, 00, 00, val], and a read
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# takes the LOW byte of the 32-bit result, so the response
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# must land in BYTE 3.
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#
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# libogc (libbba.a, gcif.o, __bba_init):
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# EXI_Imm (len=2, write) -> 42 00 the whole header
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# EXI_Sync
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# EXI_ImmEx(len=1, write) -> 00 the data
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# -> THREE bytes, data in byte 2, and a read takes byte 2.
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#
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# i.e. three bytes between CS fall and CS rise, not four. The
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# device-ID read survived the old decode only because
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# SPIMode3Slave answers it on the fast path, independently of
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# this FSM, which is why nothing caught it.
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# Both share bytes 0 and 1, so one decoder serves both:
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#
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# WRITE: latch every data byte and apply the LAST one at CS
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# rise. Swiss sends [00, val] so the last is val;
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# libogc sends [val] so the last is val. Hence NO
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# auto-increment of cmd_reg -- that would apply Swiss's
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# padding 00 to reg and val to reg+1.
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# READ : push the response TWICE so byte 2 AND byte 3 carry it.
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# Swiss clocks 4 bytes and pops both; libogc clocks 3 and
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# leaves one, which the next transaction's header pops
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# drain. A 2-byte header gives exactly one drain slot,
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# so the leftover is bounded at one and cannot build up.
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#
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# This file previously had only the 4-byte form (Swiss's), and the
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# decoder waited for a fourth byte -- so libogc's writes were
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# dropped. Changing it to libogc's form alone then broke Swiss.
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# Neither driver is "the" driver; support both.
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with m.State("CHDR_1"):
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with m.If(self.rx_rdy):
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m.d.comb += self.rx_en.eq(1)
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@@ -479,29 +496,37 @@ class BBARegisterFile(Elaboratable):
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with m.Elif(is_write):
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m.next = "CMD_WRITE"
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with m.Else():
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# Read: the response was prefetched below and the pop
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# at the end of this byte lands it in data slot 0.
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m.next = "TRAILER"
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with m.Elif(~is_write & self.tx_rdy & ~prefetched):
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# Ordinary command read: push during header byte 1 so the
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# byte-boundary pop presents it in data slot 0.
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m.next = "CMD_READ"
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with m.Elif(~is_write & self.tx_rdy & (cmd_pushes == 0)):
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# Push #1, during header byte 1, so the byte-boundary pop
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# presents it in byte 2 -- what libogc reads.
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m.d.comb += [self.tx_data.eq(rd_val), self.tx_en.eq(1)]
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m.d.sync += prefetched.eq(1)
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m.d.sync += cmd_pushes.eq(1)
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with m.State("CMD_READ"):
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# Push #2 lands in byte 3 -- what Swiss reads. It has a whole
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# byte-time to get there, unlike push #1.
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with m.If(self.tx_rdy & (cmd_pushes < 2)):
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m.d.comb += [self.tx_data.eq(rd_val), self.tx_en.eq(1)]
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m.d.sync += cmd_pushes.eq(cmd_pushes + 1)
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with m.If(self.rx_rdy):
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m.d.comb += self.rx_en.eq(1) # Swiss's padding bytes
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with m.If(~self.cs_active):
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m.next = "HEADER0"
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with m.State("CMD_WRITE"):
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# Data phase. Each byte writes the running command register,
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# which auto-increments so a multi-byte command write behaves
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# like the register-space path. cmd_wreg latches the target
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# separately because the handler below applies the write a
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# cycle later, by which time cmd_reg has already moved on.
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# Data phase. Latch each byte; the LAST one before CS rise is
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# the value, which is what lets Swiss's 4-byte form and
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# libogc's 3-byte form both decode correctly.
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with m.If(self.rx_rdy):
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m.d.comb += self.rx_en.eq(1)
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m.d.sync += [cmd_wr.eq(1),
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cmd_wdata.eq(self.rx_data),
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m.d.sync += [cmd_wdata.eq(self.rx_data),
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cmd_wreg.eq(cmd_reg),
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cmd_reg.eq(cmd_reg + 1)]
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cmd_have.eq(1)]
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with m.If(~self.cs_active):
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m.next = "TRAILER"
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with m.If(cmd_have):
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m.d.sync += cmd_wr.eq(1)
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m.next = "HEADER0"
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with m.State("TRAILER"):
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# Soak up anything else the GC clocks, then wait for CS to rise.
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@@ -882,6 +907,32 @@ if __name__ == "__main__":
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await ctx.tick("sync").repeat(6)
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return result
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async def cmd_write_swiss(ctx, creg, val):
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"""Swiss's command write: ONE 4-byte transfer
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[0x40|reg, 0x00, 0x00, val] -- exi_imm_read_write(..., 4)."""
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ctx.set(reg.cs_active, 1)
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await push_rx(ctx, 0x40 | (creg & 0x3F))
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await push_rx(ctx, 0x00)
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await push_rx(ctx, 0x00) # padding, NOT the value
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await push_rx(ctx, val) # the value is the LAST byte
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ctx.set(reg.cs_active, 0)
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await ctx.tick("sync").repeat(6)
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async def cmd_read_swiss(ctx, creg):
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"""Swiss's command read: a 4-byte read/write whose LOW byte (byte 3)
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is the response. Returns (byte2, byte3)."""
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tx_log.clear()
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ctx.set(reg.cs_active, 1)
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await push_rx(ctx, creg & 0x3F)
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for _ in range(4):
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sample_tx(ctx)
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await ctx.tick("sync")
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await push_rx(ctx, 0x00)
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got = await collect_tx(ctx, 2)
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ctx.set(reg.cs_active, 0)
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await ctx.tick("sync").repeat(6)
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return got
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# SPRAM contents the streaming-read test reads back (byte i = 0xA0+i).
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spram_mem = {0x100 + i: (0xA0 + i) & 0xFF for i in range(64)}
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@@ -1146,6 +1197,27 @@ if __name__ == "__main__":
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ctx.set(reg.tx_irq_i, 0)
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await ctx.tick("sync").repeat(2)
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# ── T12: Swiss's command-space form, which DIFFERS from libogc's ──
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# Swiss sends ONE 4-byte transfer with the value as byte 3 and reads
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# the response from byte 3; libogc sends three bytes with the value as
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# byte 2 and reads byte 2. Both are real drivers, so both must work:
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# taking the LAST data byte as the value serves both, and pushing the
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# read response twice puts it in byte 2 AND byte 3.
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#
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# Supporting only one of them is not a theoretical risk -- this file
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# had Swiss's form only (libogc's writes were dropped), then briefly
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# had libogc's form only (Swiss's writes would have been dropped).
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await cmd_write_swiss(ctx, 0x02, 0x5A)
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both = await cmd_read_swiss(ctx, 0x02)
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print(f"T12 Swiss 4-byte cmd write 0x5A -> bytes 2,3 = "
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f"{[hex(x) for x in both]}")
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if len(both) < 2 or both[1] != 0x5A:
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errors.append(f"T12 Swiss cmd form: byte 3 = "
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f"{[hex(x) for x in both]}, want 0x5A")
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if len(both) >= 1 and both[0] != 0x5A:
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errors.append(f"T12 libogc byte-2 slot also wrong: {hex(both[0])}")
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await cmd_write_swiss(ctx, 0x02, 0x00) # restore
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frame11 = [0x40 + i for i in range(24)]
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await exi_write(ctx, _TXDATA, frame11) # the frame, in ONE write
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await exi_write(ctx, _NCRA, [0x04]) # ST trigger, no TWD
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@@ -139,6 +139,35 @@ int bba_cmd_read(u8 creg)
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return (int)v;
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}
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/* SWISS's command-space form: ONE 4-byte transfer, value in byte 3, and a
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* read takes byte 3 (the low byte of the 32-bit result). Swiss's
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* bba_cmd_out8/in8 use exi_imm_read_write(..., 4).
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*
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* This DIFFERS from bba_cmd_write/bba_cmd_read above, which use libogc's
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* 2-byte-header form. Both are real drivers and the device must serve both,
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* so both shapes are exercised. */
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int bba_cmd_write4(u8 creg, u8 val)
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{
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int rc;
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u32 w = ((u32)(0x40 | (creg & 0x3F)) << 24) | val;
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if ((rc = begin_raw()) < 0) return rc;
|
||||
if (EXI_Imm(BBA_EXI_CHAN, &w, 4, EXI_WRITE, NULL) <= 0) { end_raw(); return -3; }
|
||||
if (EXI_Sync(BBA_EXI_CHAN) <= 0) { end_raw(); return -4; }
|
||||
end_raw();
|
||||
return 0;
|
||||
}
|
||||
|
||||
int bba_cmd_read4(u8 creg)
|
||||
{
|
||||
int rc;
|
||||
u32 w = ((u32)(creg & 0x3F) << 24);
|
||||
if ((rc = begin_raw()) < 0) return rc;
|
||||
if (EXI_Imm(BBA_EXI_CHAN, &w, 4, EXI_READWRITE, NULL) <= 0) { end_raw(); return -3; }
|
||||
if (EXI_Sync(BBA_EXI_CHAN) <= 0) { end_raw(); return -4; }
|
||||
end_raw();
|
||||
return (int)(w & 0xFF); /* Swiss reads the LOW byte = byte 3 */
|
||||
}
|
||||
|
||||
int bba_r8(u16 addr)
|
||||
{
|
||||
u8 v;
|
||||
|
||||
@@ -82,6 +82,12 @@ void end_raw(void);
|
||||
int bba_cmd_write(u8 creg, u8 val);
|
||||
int bba_cmd_read(u8 creg);
|
||||
|
||||
/* Swiss's command-space form: ONE 4-byte transfer, value/response in byte 3.
|
||||
* Differs from bba_cmd_write/read above (libogc's 2-byte-header form); the
|
||||
* device must serve both. */
|
||||
int bba_cmd_write4(u8 creg, u8 val);
|
||||
int bba_cmd_read4(u8 creg);
|
||||
|
||||
/* Convenience single-byte helpers. bba_r8 returns the byte, or <0 on error. */
|
||||
int bba_r8(u16 addr);
|
||||
int bba_w8(u16 addr, u8 val);
|
||||
|
||||
@@ -421,6 +421,30 @@ static int t_cmd_write(char *m, size_t n)
|
||||
return rb == 0x00 ? 0 : 1;
|
||||
}
|
||||
|
||||
static int t_cmd_write_swiss(char *m, size_t n)
|
||||
{
|
||||
int rc, rb;
|
||||
/* Swiss sends ONE 4-byte transfer with the value as byte 3 and reads the
|
||||
* response from byte 3; libogc (and libogc2) send a 2-byte header plus a
|
||||
* data phase, value in byte 2. Both are real drivers. The device takes
|
||||
* the LAST data byte as the value and pushes a read response twice, so
|
||||
* bytes 2 and 3 both carry it -- this test is the Swiss half. */
|
||||
if ((rc = bba_cmd_write4(0x02, 0x5A)) < 0) {
|
||||
snprintf(m, n, "Swiss cmd write failed: EXI error %d", rc); return 1;
|
||||
}
|
||||
if ((rb = bba_cmd_read4(0x02)) < 0) {
|
||||
snprintf(m, n, "Swiss cmd read failed: EXI error %d", rb); return 1;
|
||||
}
|
||||
if (rb != 0x5A) {
|
||||
snprintf(m, n, "Swiss 4-byte form: wrote 0x5A, byte 3 = 0x%02X", rb);
|
||||
bba_cmd_write4(0x02, 0x00);
|
||||
return 1;
|
||||
}
|
||||
bba_cmd_write4(0x02, 0x00);
|
||||
snprintf(m, n, "4-byte form ok (byte 3 = 0x%02X)", rb);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int t_mac_is_readable(char *m, size_t n)
|
||||
{
|
||||
u8 mac[6];
|
||||
@@ -654,6 +678,7 @@ static test_t s_spram[] = {
|
||||
|
||||
static test_t s_init[] = {
|
||||
{"cmd-space write","2-byte header + data phase, as libogc sends it", t_cmd_write, T_PENDING, {0}},
|
||||
{"cmd-space Swiss","4-byte transfer, value in byte 3, as Swiss sends", t_cmd_write_swiss, T_PENDING, {0}},
|
||||
{"MAC readable", "libogc READS the MAC from PAR0-5; it must be sane", t_mac_is_readable, T_PENDING, {0}},
|
||||
{"init replay", "libogc's 30 init writes, in order, do no harm", t_init_sequence, T_PENDING, {0}},
|
||||
{"TX without TWD","libogc never writes TWD; length must be counted", t_tx_no_twd, T_PENDING, {0}},
|
||||
@@ -666,7 +691,7 @@ suite_t g_suites[] = {
|
||||
{"EXI integrity", "the EXI link is error-free, and how fast", s_exi, 6},
|
||||
{"Ethernet", "frames get to and from the W5100", s_eth, 3},
|
||||
{"SPRAM/DMA", "bulk reads stream correctly from the ring", s_spram, 2},
|
||||
{"libogc init", "the real driver's init sequence and shapes", s_init, 4},
|
||||
{"driver shapes", "Swiss + libogc init sequences and transfer shapes", s_init, 5},
|
||||
};
|
||||
const int g_nsuites = sizeof(g_suites) / sizeof(g_suites[0]);
|
||||
|
||||
|
||||
Reference in New Issue
Block a user