Fixes the GC/USB power led handover
This commit is contained in:
@@ -69,7 +69,7 @@ the impedance-matching resistors — wrong part for an LED.) The RGB LED
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part of this complaint. BOM/PCB change for V2; a rework could tack larger
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resistors on this unit if the brightness is a bench nuisance.
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### 2. GC_ON is not the clean on/off the gateware assumed (sits at 2.3 V; both handover LEDs on)
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### 2. GC_ON was not a clean on/off (sat at 2.3 V; both handover LEDs on) — FIXED in schematic 2026-08-28
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**Observation:** `GC_ON` measures **2.3 V** (not a clean rail). With **both USB
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and GC connected**, both transistor-driven LEDs (D8, D9) are lit — the intent
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@@ -83,17 +83,29 @@ U12.3, FPGA **U9 pin 21**, pulled up by R5 10 k to 3V3; drives Q1 base via R39
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when base ≲2.6 V) **both conduct** → both D8 and D9 light. There is no clean
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one-or-the-other point at this intermediate voltage.
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**Two things to resolve:**
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- **Hardware:** the complementary-transistor indicator doesn't give a clean
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handover display at the actual GC_ON level. Re-think for V2 (e.g., a comparator
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/ proper level, or drive the two indicators from a real one-hot power-source
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signal). First confirm what GC_ON's ST pin actually does across the USB-only /
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GC-only / both states (TPS2116 ST semantics — see REVIEW.md).
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- **Gateware:** GC_ON is wired to FPGA pin 21 but **not yet used**. The planned
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"gate all outputs on GC_ON" (see TODO.md) assumed GC_ON is a clean logic level.
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2.3 V is above the iCE40 3.3 V-LVCMOS V_IH (~2.0 V) so pin 21 would read HIGH,
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but it's marginal and the semantics aren't the assumed on/off. Verify the real
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signal before relying on it for output gating.
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**Root cause (identified 2026-08-28):** the intermediate ~2.3 V is **base-loading
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of the open-drain ST node**. When GC is the source, ST is Hi-Z and *should* sit at
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3V3 (R5 pull-up), but Q1's base (through R39 10 k) drags it down — R5‖R39 divide
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3V3 to ~2.0 V — which is low enough that the PNP Q2's V_EB ≈ 1.3 V and it conducts
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too. So both LEDs light, and the FPGA/EN see a soggy 2 V instead of 3V3.
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TPS2116 ST is only characterised to sink **1 mA** (DS: V_OL @ I_ST = 1 mA,
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t_ST @ R_ST = 10 k), so simply strengthening R5 is not allowed.
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**Hardware fix — APPLIED 2026-08-28 (schematic):** raise the base resistors and
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modestly lower the pull-up so GC_ON swings clean while ST stays ≤1 mA:
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- **R5 10 k → 5.1 k** (C25905, reuses R6/R7 part)
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- **R39 / R40 10 k → 33 k** (C25779, reuses R1 part)
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Result: GC active → GC_ON ≈ **2.95 V** → Q1 saturates (D8/GC lit), Q2 V_EB ≈
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0.35 V → OFF (D9/USB dark); USB active → ST low (sinks ~0.73 mA < 1 mA) → D9 lit,
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D8 dark. Clean one-hot. **No new BOM lines, no PCB layout change** (resistor value
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swaps only — run "Update PCB from Schematic" so the F.Fab values match). This also
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**resolves the gateware concern below**: GC_ON now reads a solid ~2.95 V (well
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above the iCE40 V_IH) instead of a marginal 2.3 V. D8/D9 = GC/USB is the confirmed
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assignment (TPS2116 ST "low when VIN1 not used", VIN1 = GC priority — see
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REVIEW.md); the B.SilkS labels are correct.
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- ~~**Gateware:** GC_ON marginal at 2.3 V for the FPGA pin-21 read~~ — addressed
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by the fix above (now ~2.95 V). The "gate all outputs on GC_ON" work (TODO)
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can now assume a clean level; still verify on the reworked bench unit.
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### 3. Functional W5100 test — send a packet capturable in Wireshark (works around broken D3?)
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@@ -5314,7 +5314,7 @@
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(justify left)
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)
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)
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(property "Value" "10k"
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(property "Value" "33k"
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(at 62.23 61.15 0)
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(show_name no)
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(do_not_autoplace no)
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@@ -5358,7 +5358,7 @@
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)
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)
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)
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(property "MPN" "0402WGF1002TCE"
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(property "MPN" "0402WGF3302TCE"
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(at 62.23 57.15 0)
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(hide yes)
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(show_name no)
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@@ -5369,7 +5369,7 @@
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)
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)
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)
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(property "LCSC" "C25744"
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(property "LCSC" "C25779"
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(at 62.23 57.15 0)
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(hide yes)
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(show_name no)
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@@ -7314,7 +7314,7 @@
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(justify left)
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)
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)
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(property "Value" "10k"
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(property "Value" "5.1k"
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(at 132.08 44.45 0)
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(show_name no)
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(do_not_autoplace no)
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@@ -7358,7 +7358,7 @@
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)
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)
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)
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(property "MPN" "0402WGF1002TCE"
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(property "MPN" "0402WGF5101TCE"
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(at 0 0 0)
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(hide yes)
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(show_name no)
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@@ -7380,7 +7380,7 @@
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)
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)
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)
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(property "LCSC" "C25744"
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(property "LCSC" "C25905"
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(at 0 0 0)
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(hide yes)
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(show_name no)
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@@ -8143,7 +8143,7 @@
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(justify left)
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)
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)
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(property "Value" "10k"
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(property "Value" "33k"
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(at 17.78 72.58 0)
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(show_name no)
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(do_not_autoplace no)
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@@ -8187,7 +8187,7 @@
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)
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)
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)
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(property "MPN" "0402WGF1002TCE"
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(property "MPN" "0402WGF3302TCE"
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(at 17.78 68.58 0)
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(hide yes)
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(show_name no)
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@@ -8198,7 +8198,7 @@
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)
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)
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)
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(property "LCSC" "C25744"
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(property "LCSC" "C25779"
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(at 17.78 68.58 0)
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(hide yes)
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(show_name no)
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@@ -42,6 +42,15 @@ datasheet extraction, WebSearch/WebFetch for parts and reference designs.
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FPGA-GC_ON use. USB-only fallback verified via truth table (MODE≤0.35 V row).
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PR1 divider was marginal (1.10 V vs VREF 1.0±8 %) → **fixed: R3=150k**
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(switchover 2.30–2.70 V). Abs max (6 V) fine.
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**D8/D9 handover-indicator base-loading fixed 2026-08-28:** the complementary
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Q1(NPN)/Q2(PNP) indicator bases hung on the open-drain ST/GC_ON node through
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R39/R40 10 k; with R5 10 k they divided GC_ON to ~2 V on GC power, turning BOTH
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LEDs on and giving the FPGA/EN a soggy level (BRINGUP #2). ST is only
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characterised to 1 mA sink, so R5 can't just be strengthened. Fix: **R5 10k→5.1k
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(C25905), R39/R40 10k→33k (C25779)** → GC_ON ≈ 2.95 V on GC (Q1 sat / Q2 off,
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D8=GC only), ST sinks ~0.73 mA on USB (Q2 on, D9=USB only). Clean one-hot;
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reuses existing parts; no PCB layout change. D8=GC / D9=USB assignment confirmed
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(ST low when VIN1 not used, VIN1=GC priority).
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- **AP2112K-1.2 (U1) / AP2112K-3.3 (U4)**: 1 µF X5R in/out present (DS
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requirement), 600 mA rating vs load fine, dropout headroom checked (1.2 V
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version has 1.0–1.3 V dropout — OK from 3.3 V), EN=VIN OK.
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+16
-18
@@ -143,24 +143,22 @@ Cosmetic/mechanical items for the in-progress V2 rework (EEPROM→93LC56B,
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reverse-mount LEDs, J3 slot already done). These are PCB-layout tasks, not
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schematic changes.
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- [ ] **1. Add the project name in silkscreen.** Put a "re-bba-rb" (or chosen
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project name/version) label on the board silkscreen so the assembled board
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is identifiable. Pick a copper-free spot; watch the JLC 1.0 mm min text
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height / 0.15 mm min line-width floor (same rule that just caught the LED
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refdes). Consider adding a small rev tag (e.g. "v2") next to it.
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- [ ] **2. Extend the board out to the ethernet socket so it sits flush with the
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GC.** Lengthen the board outline (Edge.Cuts) toward the RJ45/magjack (J2)
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end so the finished board reaches flush with the GameCube's shell instead
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of stopping short. Mechanical-only (move the board edge + any ground pour
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to suit); keep the SP1/J3 edge geometry fixed. Verify the new outline
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against the GC slot depth before ordering.
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- [ ] **3. Add back-side silkscreen legends for the LEDs.** Label what each LED
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means on **B.SilkS** (the back is the viewing side — reverse-mount LEDs
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emit through the board, top faces into the GC slot). Map from the current
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build: LEDG/D6 = heartbeat, LEDR/D7 = EXI activity, RGB D11 = rx / D12 =
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tx / D13 = ready, D8/D9 = USB/GC power handover indicators. Confirm the
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final per-LED meaning against `synth.py` + BRINGUP.md before lettering, and
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mind the same silk text-height/width floor as item 1.
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- [x] **1. Add the project name in silkscreen — DONE 2026-08-28** (commit
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"Added Silkscreen labels"). "ReBBArb V2" (2 mm) on B.SilkS, mid-board.
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Free-floating over some copper (silk_over_copper warning, JLC clips it) —
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reposition to taste if wanted.
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- [ ] ~~**2. Extend the board to the ethernet socket for a flush GC fit.**~~
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**DROPPED 2026-08-28** — Dennis decided against extending the outline;
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board ships at its current length.
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- [x] **3. Back-side silkscreen LED legends — DONE 2026-08-28** (same commit).
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On B.SilkS (mirrored): RX (D11) / TX (D12) / RDY (D13) / HB (D6, heartbeat)
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/ EXI (D7) as vertical labels above the LED-window row; USB (D9) / GC (D8)
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above the two power LEDs. Semantics confirmed against `synth.py`.
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D8/D9 = GC/USB assignment **confirmed** (TPS2116 ST low when VIN1 not used,
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VIN1 = GC priority) and the handover indicator **circuit fixed** 2026-08-28
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(R5 10k→5.1k, R39/R40 10k→33k — see BRINGUP #2 / REVIEW.md), so the labels
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are correct and the indicator is now clean one-hot. "ReBBArb V2" name
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position confirmed fine by Dennis.
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## Critical — ALL RESOLVED (schematic + PCB, verified 2026-07-18)
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@@ -3603,7 +3603,7 @@
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)
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)
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)
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(property "Value" "10k"
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(property "Value" "33k"
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(at 0 1.17 90)
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(layer "F.Fab")
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(uuid "660266f2-d8cd-4e63-bc1a-418e418c2d76")
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@@ -3661,7 +3661,7 @@
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)
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)
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)
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(property "LCSC" "C25744"
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(property "LCSC" "C25779"
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(at 0 0 90)
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(unlocked yes)
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(layer "F.Fab")
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@@ -17797,7 +17797,7 @@
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)
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)
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)
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(property "Value" "10k"
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(property "Value" "5.1k"
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(at 0 1.17 90)
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(layer "F.Fab")
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(uuid "ccf842e5-1b0d-43e6-981b-8fb93f841dfa")
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@@ -17869,7 +17869,7 @@
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)
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)
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)
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(property "LCSC" "C25744"
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(property "LCSC" "C25905"
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(at 0 0 270)
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(unlocked yes)
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(layer "F.Fab")
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@@ -23573,7 +23573,7 @@
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)
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)
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)
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(property "Value" "10k"
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(property "Value" "33k"
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(at 0 1.17 90)
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(layer "F.Fab")
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(uuid "7696d858-4c8e-46b2-97a0-f6d71e0d1f1b")
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@@ -23631,7 +23631,7 @@
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)
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)
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)
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(property "LCSC" "C25744"
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(property "LCSC" "C25779"
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(at 0 0 90)
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(unlocked yes)
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(layer "F.Fab")
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