Fixes the GC/USB power led handover

hardware/re-bba-rb/REVIEW.md

@@ -42,6 +42,15 @@ datasheet extraction, WebSearch/WebFetch for parts and reference designs.
   FPGA-GC_ON use. USB-only fallback verified via truth table (MODE≤0.35 V row).
   PR1 divider was marginal (1.10 V vs VREF 1.0±8 %) → **fixed: R3=150k**
   (switchover 2.30–2.70 V). Abs max (6 V) fine.
+  **D8/D9 handover-indicator base-loading fixed 2026-08-28:** the complementary
+  Q1(NPN)/Q2(PNP) indicator bases hung on the open-drain ST/GC_ON node through
+  R39/R40 10 k; with R5 10 k they divided GC_ON to ~2 V on GC power, turning BOTH
+  LEDs on and giving the FPGA/EN a soggy level (BRINGUP #2). ST is only
+  characterised to 1 mA sink, so R5 can't just be strengthened. Fix: **R5 10k→5.1k
+  (C25905), R39/R40 10k→33k (C25779)** → GC_ON ≈ 2.95 V on GC (Q1 sat / Q2 off,
+  D8=GC only), ST sinks ~0.73 mA on USB (Q2 on, D9=USB only). Clean one-hot;
+  reuses existing parts; no PCB layout change. D8=GC / D9=USB assignment confirmed
+  (ST low when VIN1 not used, VIN1=GC priority).
 - **AP2112K-1.2 (U1) / AP2112K-3.3 (U4)**: 1 µF X5R in/out present (DS
   requirement), 600 mA rating vs load fine, dropout headroom checked (1.2 V
   version has 1.0–1.3 V dropout — OK from 3.3 V), EN=VIN OK.