Commit Graph

18 Commits

Author SHA1 Message Date
Dennis Brentjes 5828d6a388 Finished the board including the connector and mousebites 2026-07-24 14:04:04 +02:00
Roflin a86aa255f1 Add REVIEW.md: complete hardware-review coverage record
Documents everything examined in the 2026-07-17/18 review - not just
findings but full coverage with verdicts, so future sessions know what
not to re-review: per-sheet verification against datasheets and the
WIZnet reference design, the settled look-wrong-but-correct list
(VPHY/VPLL on 3.3V, D4/D5 floating VBUS + flow-through, EN at 12V,
RSET 12.4k, no CT cap, DO/DI direction evidence), PCB/JLC/BOM audit
state, explicit not-reviewed list (bench/gateware items), and a binding
rule to keep the file updated in the same commit as any change to a
reviewed circuit. Referenced from CLAUDE.md alongside TODO.md.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
2026-07-20 20:21:39 +02:00
Roflin 3905319aea PCB: insert MDI dampers R32-R35 in-line and place C20/C21 at J2 center taps
Insertion by Dennis; reviewed:
- DRC 0 errors / 0 unconnected / 0 schematic parity
- R32-R35 sit in-line between the termination cluster and D4/D5, each
  aligned to its own line row; MDI_* stubs only 1.45-1.48mm, no new
  vias, all pair copper at the ETH_DP 0.2mm width
- Pair skew after insertion: TX 0.66mm, RX 1.81mm - both far inside
  the 100BASE-TX budget
- C20/C21 placed against J2's pin column, about as close as the In1
  plane void allows while keeping short GND vias

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
2026-07-18 14:10:23 +00:00
Roflin ad37ebda87 Ethernet: add 3.3R MDI dampers (R32-R35) and J2 center-tap bypass (C20/C21)
Completes the WIZnet reference schematic for the MDI section:
- R32-R35 3.3R 1% (YAGEO RC0402FR-073R3L, LCSC C137986) in series in
  each MDI line per WIZnet note 6 (EMI damping). Chain per line is now
  U11 pin -> 49.9R termination tap -> 3.3R -> D4/D5 flow-through -> J2.
  Chip-side nets keep PHY_*; the D4/D5-side segments are renamed MDI_*
  and added to the ETH_DP netclass patterns so the impedance DRC rules
  police both halves.
- C20 100nF (C1525) + C21 1uF (C15849) on ETH_3V3 per WIZnet note 7 -
  to be placed AT J2 pins 4/5 tapping the In2 ETH_3V3 island.

(Also carries KiCad's resave/reposition of ethernet.kicad_sch from the
rework session - netlist-identical, verified.)

Verified: ERC 0, netlist 121 components vs BOM 120 (J3-only delta),
PHY_TX_P = {U11.3, R26.1, R32.1}, MDI_TX_P = {R32.2, D4.1}, and
likewise for all four lines. PCB: 6 footprints to place (cut the lines
between termination and D4/D5 for R32-R35; C20/C21 at the jack).

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
2026-07-18 14:01:16 +00:00
Roflin 3547302ec2 Finished the PCB design 2026-07-17 21:35:02 +02:00
Roflin 4b2f7be7d8 Made pcb with single ground plane 2026-07-11 23:55:48 +02:00
Dennis Brentjes 5727fc74a3 Fixes the power traces. 2026-07-09 20:08:05 +02:00
Dennis Brentjes 620ae5cd64 finalized pcb design, need to remeasure PCB outline. 2026-07-08 22:00:53 +02:00
Dennis Brentjes 4e7853351c Everything on the board. still missing some decoupling caps. 2026-07-05 21:49:57 +02:00
Roflin 3142e3bd59 Rework the PCB. 2026-07-04 20:00:02 +02:00
Roflin e18b200c37 Reworked power section to fit the exi traces. 2026-07-04 11:41:49 +02:00
Roflin b4c2a53a9b Reworked the footprints. 2026-07-03 17:06:01 +02:00
Roflin 857c428031 Played around with board shape/layout Changed USB power tree 2026-06-26 22:07:59 +02:00
Roflin 298804d3dd Finished rest of the schematics. 2026-06-20 11:55:39 +02:00
Dennis Brentjes 079f3eed94 Started working on FPGA sheet. 2026-06-18 16:38:23 +02:00
Dennis Brentjes a6a6aa37e0 Added Usb sheet 2026-06-17 21:37:49 +02:00
Roflin 056557345f Adds a power_sch 2026-06-16 14:59:18 +02:00
Roflin a7c88109a9 Started on component selection of the final PCB. 2026-06-13 22:09:05 +02:00