Commit Graph

10 Commits

Author SHA1 Message Date
Roflin 530f41cf7a Add FT2232H EEPROM interface resistors per datasheet Table 3.4
The 93LC46B's DO and DI were both tied directly to EEDATA, causing
drive contention during EEPROM read turnaround. Per the FT2232H
datasheet ("Connect directly to Data-In of the EEPROM and to Data-Out
of the EEPROM via a 2.2K resistor. Also, pull Data-Out of the EEPROM
to VCC via a 10K resistor"):

- U7.4 (DO) moved onto new net EE_DO
- R30 2.2k (UNI-ROYAL 0402WGF2201TCE, LCSC C25879, Basic) between
  EE_DO and EE_DATA
- R31 10k (0402WGF1002TCE, C25744) pull-up from EE_DO to 3V3
- EEDATA -> DI (U7.3) stays direct

Schematic only; R30/R31 still need placing near U7 in the PCB rework.
Verified: ERC 0, EE_DATA = {U8.61, U7.3, R30.2}, EE_DO = {U7.4, R30.1,
R31.2}, R31.1 on global /Power/3V3 (no orphan local net), netlist
115 vs BOM 114 differing only by the deliberate J3 exclusion.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
2026-07-18 12:51:54 +00:00
Roflin 3547302ec2 Finished the PCB design 2026-07-17 21:35:02 +02:00
Roflin 4b2f7be7d8 Made pcb with single ground plane 2026-07-11 23:55:48 +02:00
Dennis Brentjes 620ae5cd64 finalized pcb design, need to remeasure PCB outline. 2026-07-08 22:00:53 +02:00
Dennis Brentjes 4e7853351c Everything on the board. still missing some decoupling caps. 2026-07-05 21:49:57 +02:00
Roflin b4c2a53a9b Reworked the footprints. 2026-07-03 17:06:01 +02:00
Roflin 61641de40b Started on a 4 layer board with cutout for interposer 2026-06-27 22:25:03 +02:00
Roflin 857c428031 Played around with board shape/layout Changed USB power tree 2026-06-26 22:07:59 +02:00
Roflin 298804d3dd Finished rest of the schematics. 2026-06-20 11:55:39 +02:00
Dennis Brentjes a6a6aa37e0 Added Usb sheet 2026-06-17 21:37:49 +02:00